Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon. Gates. W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo and M.-R.
Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon Gates W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo and M.-R. Lin AMD, Technology Research Group Sunnyvale, CA 94088, USA Abstract Metal gate electrodes with two different work functions, ~4.5 and ~4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was ~0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same Toxinv as poly gate. Introduction Replacing polysilicon gate electrodes in MOSFETs with metal ones promises three distinct advantages: I. improved sheet resistance of the gate, particularly of interest in AC performance; II. decrease of equivalent electrical thickness of gate dielectric, Toxinv (extracted from gate capacitance in inversion bias). This is accomplished by elimination of polysilicon gate depletion effect. Excessive tunneling current through gate dielectric (~100 A/cm2) stops the scaling of gate oxide thickness around 12-14 A (1). Elimination of polysilicon depletion allows to scale down Toxinv by several Angstroms without decreasing the physical thickness of the oxide and possibly with lesser increase in its tunneling current. III. choice of work function. Higher than n+ poly work function for NMOS and lower than p+ poly for PMOS would avoid excessive dopant density in the channel, necessary to control off-current in highly scaled devices. This would lessen drive current loss due to mobility degradation and decrease the chance for band-to-band tunneling across drain-to-body junction. Simplification of process integration would require single metal to be used for both NMOS and PMOS transistors. However, such material would have to have work function around silicon’s mid gap value of ~4.6-4.7 eV to provide symmetric benefit to both types of transistors. Such work function would contribute to too high threshold voltages to be acceptable for high performance logic applications. To maintain performance advantage in highly scaled devices, below Lgate~30-40 nm, gate electrodes with two distinct work functions will be needed. Acceptable range of work functions appears to be ~4.1 - 4.4eV for NMOS and 4.8 – 5.1 eV for PMOS (2). There are only a few candidates for the electrodes such as Ta, TaN, Nb for NMOS and WN, RuO2 for PMOS, and their implementation requires complex processing. Gate-last approach utilizing damacsene/replacement technique avoids difficult issues
related to high temperature budget, contamination and metal etching and is most likely to be utilized for this dual-metal approach. A single metal alternative has been explored, where implantation of nitrogen has successfully modified work function of molybdenum making it attractive for dualwork function metal gate CMOS applications (3). Thick oxide (7 nm) capacitor data with fully silicided (FUSI) polysilicon gates has been recently reported for NiSi where two different work functions were found for n+ and p+ poly (4). Transistor data was also reported for FUSI gates with CoSi2 (5), where only a single, mid-gap work function resulted. In this work we present dual-work function metal gate NMOS and PMOS SOI transistors with gates formed by a single step full silicidation (FUSI) of polysilicon gates with nickel, and we discuss the origins of the dual work function fenomenon. We believe this is the first demonstration of such transistors. We also discuss limited benefits of metal gates in terms of gate leakage reduction. Experiment Conventional CMOS transistors with 1.7 nm equivalent oxide thickness (EOT) nitride/oxide dielectric stack and polysilicon gates were built. No channel doping was utilized. Polysilicon gates were doped with B and As for PMOS and NMOS, respectively. Source/drain and gates were silicided with nickel. Ni thickness varied from 15-40 nm, with the thickest films expected to fully silicide the 70 nm thick poly. Use of SOI substrate prevented deep junction shorts under the
gate
SOI
BOX
Fig. 1 TEM cross section of transistor with fully silicided gate electrode.
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deep silicide contacts. Additional gate spacers were placed after deep s/d implants and before silicidation to minimize the chance for thick s/d silicide shorting the lateral part of the junctions.
Electrical Results C-V measurements on large (100x100 µm) capacitors show that for samples with up to 30 nm of Ni the shape of CV curves remains unchanged indicating that NiSi is sufficiently far from the gate dielectric not to effect capacitor’s electrical properties. For 35 and 40 nm thick Ni, C-V curves progressively shift toward higher voltages in NMOS and lower voltages in PMOS, in week inversion regime (Fig. 2, 3). As expected, Id-Vg curves shifted
1.00E-02
1.00E-03
Ni thickness
1.00E-04 Id [A]
Structural Results Cross-section TEM images (Fig.1) confirmed that transistors that received 40 nm of Ni have been fully silicided. EELS mapping of TEM cross-sections confirmed the presence of NiSi. As expected, thinner Ni films resulted with incomplete silicidation of the poly.
NMOS IdVg @ Vd=0.1V L/W=0.5/400um
1.00E-05
Ni=200A Ni=250A Ni=300A Ni=350A Ni=400A
1.00E-06
1.00E-07 -2
-1.5
-0.5
0
0.5
1
Fig. 4. NMOS IdVg curves at Vd=0.1V for different NiSi thicknesses.
PMOS IdVg @Vd=0.1V L/W=0.38/400um 1.E-02
Ni=150A Ni=200A Ni=250A Ni=300A Ni=350A Ni=400A
Tox=17A N/O EOT
1.4E-06
1.E-03 Ni=200A Ni=250A Ni=300A Ni=350A Ni=400A
1.0E-06 8.0E-07 6.0E-07
1.E-04 Id [A]
1.2E-06
Ni thickness
1.5
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NMOS C-V 1.6E-06
C [F/cm2]
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1.E-05 1.E-06 1.E-07
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0.0E+00
1.E-08 -0.5 0
0.5
1
1.5
Vg [V] -2
-1
0
1
2
Vg [V]
Fig. 5. PMOS IdVg curves at Vd=-0.1V for different NiSi thicknesses.
Fig. 2. C-V curves for large NMOS capacitors with different thickness of NiSi.
0.4
PMOS C-V
NMOS Vd= -0.1V
0.2
1.6E-06
Vtlin [V]
Tox=17A N/O EOT
1.4E-06
Ni=150A Ni=200A Ni=250A Ni=300A
1.2E-06 Cg [F/cm2]
PMOS
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4.0E-07
0.0E+00 -1
0
1
-0.4 -0.8 100
2.0E-07 -2
-0.2 -0.6
Ni=350A Ni=400A
6.0E-07
0
Fig. 3. C-V curves for large PMOS capacitors with different thickness of NiSi.
200
300
400
500
Ni thickness [A]
2
Vg [V]
Vd= 0.1V
Fig. 6. NMOS and PMOS linear Vt dependence on amount of poly gate silicidation.
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100
Toxinv vs. Ni thickness NMOS PMOS
30
Tox inv. [A]
28 26 24
Atomic Concentration (%)
90
NiSi
80 70 60
Ni
50 40
Gate oxygen
30
22
SOI
20
boron x 20
10
20 100
200 300 400 Ni thickness [A]
500
00
200 400 600 800 1000 1200 1400 1600 1800 2000 Sputter Time (s)
Fig. 7. Elimination of poly gate depletion by full silicidation of the gate.
Fig. 9. Auger profiles of B, Ni, Si and O. Full silicidation of the p+ poly gate and pile-up of B on the top of gate dielectric is evident.
similarly to the flat band shift observed in C-V curves: toward higher Vg values for NMOS (Fig. 4) and lower for PMOS (Fig. 5) for Ni film thickness about 30 nm or more. NMOS linear Vt increased about 400 mV and PMOS Vt decreased by ~200 mV for samples with 40 nm thick nickel (Fig. 6). Assuming the Vt shift is caused by work function change alone, we can estimate that the NMOS work function is ~4.5 eV and PMOS ~4.9 eV. This relates closely to the findings of ref. (4), 4.6 eV for n+ and 5.0 eV for p+ poly, where n-type capacitors were doped with phosphorous instead of arsenic. The C-V curves also show progressive increase in Cinv for Ni thicker than 30 nm. This indicates reduction of poly depletion. Calculated values of Toxinv show that the reduction of poly depletion amounts to ~0.25 nm for both NMOS and PMOS (Fig. 7).
Chemical Analysis Auger and SIMS profiles confirmed that NiSi extends throughout the full thickness of the electrode, and the dopants, originally present in the polysilicon gates, have been segregated (“snow-ploughed”) in front of the advancing silicide front. The amount of piled-up arsenic at the top of gate dielectric is a significant fraction of ~1 nm thick Ni-SiAs film (Fig. 8). With over 50% of the implanted As dose (4*1015 cm-2) present in that peak, metallic arsenic likely dominates the content of that film, helping to modify the work function of pure NiSi, reported to be 4.9 eV (4). There is much less of boron accumulated at the gate dielectric/electrode interface in PMOS (Fig. 9), apparently insufficient to modulate the NiSi work function. Our calculated value of PMOS gate electrode work function was found close to the pure NiSi value.
100
Atomic Concentration (%)
90 80
NiSi
70 60
SOI Ni
50 Gate oxygen
40 30
arsenic x 20
20 10 0
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Sputter Time (s)
Gate Tunneling Current Measurements of gate tunneling current show no major issues with the dielectric integrity (Fig. 10). However, when current is measured for the same gate overdrive, Vg-Vt, to accommodate threshold shift due to work function change, the current in FUSI gates biased in inversion is found higher by about an order of magnitude than in the control poly gates (Fig. 11). This current increase is similar to what one would expect from ~0.2 nm decrease of physical thickness of the gate dielectric (6), suggesting little benefit from reduced poly depletion in highly scaled devices, i.e. leakage current will be similar for FUSI gates and for poly gates with the same Vt and Toxinv (Fig.12). Simulations of tunneling gate current through thin SiO2 with metal and poly gate electrodes (using NEMO program (7)) show that when compared to polysilicon gate doped at or above 5*1020 cm-3, metal gates do not offer any gate current benefits at the same Toxinv (Fig. 13).
Fig. 8. Auger profiles of As, Ni, Si and O. Full silicidation of the n+ poly gate and significant pile-up of As on the top of gate dielectric is evident.
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Summary Reduction of polysilicon depletion by ~0.25 nm and metal gate electrodes with two different work functions were obtained by full silicidation of poly gates. The values of work functions were ~4.5 and ~4.9 eV for NMOS and PMOS, respectively. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same Toxinv as poly gate.
References (1) (2) (3) (4) (5) (6) (7)
T.Ghani et al., Symp. VLSI Tech. Dig. p. 174, 2000. B.Cheng et al, IEEE Intl.SOI Conf.Proc., p. 91, 2001 Q.Lu et al., Sump.VLSI Tech.Dig., p. , 2001. M.Qin et al., J.Electrochem.Soc., 148(5), p. G271, 2001. B.Tavel et al., IEEE Tech.Dig., p. , 2001. S.-H.Lo et al., IEEE El.Dev.Lett., 18, p.209, 1997. Program described in: D. K. Blanks et al., “NEMO: General release of a new comprehensive quantum device simulator,” in Proceedings of IEEE 24th International Symposium of Compound Semiconductors, 1998, pp. 639-642
0.1
NMOS Vg-Vt=0.9V
Gate current density 0.08 2
Jg [A/cm ]
Gate current density [A/cm2]
1.E+01 1.E+00 1.E-01
FUSI gates 0.06 poly gates
0.04 0.02
1.E-02 15 nm of Ni 40 nm of Ni
1.E-03
0 10
20
30
40
50
Ni thickness [nm] 1.E-04 0
1
2
3
Gate voltage [V]
Fig. 11. NMOS gate current density at the Vg-Vt=0.9V for different amounts of gate silicidation.
Fig. 10. NMOS gate current density for reference and fully silicided gates shows very similar behavior.
NMOS Vg-Vt=0.9V
6
10
5
10
4
10
3
10
2
10
1
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0
5E19 1E20 5E20 1E21 Metal
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JG [A/cm ]
Gate current density [A/cm2]
0.1
10
0.01
FUSI gates
model poly gates
-1
10
-2
10
0.001 2.4
2.6
2.8
3
NEMO Simulation VG-VT=0.9V 1
2
3
Toxinv [nm]
Toxinv [nm]
Fig. 12. NMOS gate current density vs. gate dielectric thickness (Toxinv.) for Vg-Vt=0.9V. Combines data from Fig.7 and 11. Dashed line indicates simulated current for poly gate.
Fig. 13. Simulated gate tunneling current for SiO2 with metal and poly gate electrodes vs. Toxinv shows no current benefit of metal gate when compared to highly doped poly gate.
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