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The devices have a gate length of Lg = 2 µm and a width of Wg = 40 µm. 3. Results and discussion ... For each oxide thickness, the flatband volt- age has been ...

J O U R N A L O F M A T E R I A L S S C I E N C E : M A T E R I A L S I N E L E C T R O N I C S 1 6 (2 0 0 5 ) 433 – 436

Tungsten work function engineering for dual metal gate nano-CMOS J. K. EFAVI, T. MOLLENHAUER, T. WAHLBRINK, H. D. B. GOTTLOB, M. C. LEMME, H. KURZ Advanced Microelectronic Center Aachen, AMO GmbH, Huyskensweg 25, 52074 Aachen, Germany E-mail: [email protected] A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx ) as a buffer layer on silicon dioxide (SiO2 ) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are C 2005 Springer Science + Business Media, Inc. presented. 

loy during subsequent annealing without increasing the equivalent oxide thickness (EOT), and must result in a work function suitable for CMOS integration [9]. AlNx has been reported to posses all these qualities [10]. We report for the first time results of using AlNx to tune the work function of tungsten as a metal gate material suitable for p-MOSFETs. This work therefore paves the way for tungsten to be used as p-type material together with other metals such as Ta (4.4 e.V) and Hf (3.9 eV) which have been reported to be n-type using similar technology in dual metal gate CMOS integration [9]. This paper describes the fabrication and characterization of MOS-Capacitors with a SiO2 /AlNx /W gate stack. The main focus has been put on the metal/dielectric interface properties, the interface charge passivation in subsequent process steps and the work function of the material compared to pure W. The results obtained from MOS-capacitors have been used to fabricate and characterize p-MOSFETs.

1. Introduction Metal gate materials for CMOS-technology are currently subject of great research interest to meet the demanding targets set by the International Technology Roadmap for Semiconductors (ITRS) [1]. Metal gate technology is proposed to eliminate effects such as poly silicon depletion, poly silicon dopant penetration and subsequent gate leakage as device miniaturization continues [2–4]. The variety of candidate materials can be divided into three groups: universal mid-gap metals, dual work function metals and single metals with tunable work functions. A disadvantage of universal mid-gap metals is the unacceptably high threshold voltage for n- and pMOSFETs, respectively [5]. Two different metals for nand p-type devices require additional lithographic steps and twice the effort to solve material integration issues. Such technology also results in dielectric integrity problems due to removal of the metal deposited first [6]. The work function of a single metal can be tuned by ion implantation. While simple to carry out, this process results in increased gate leakage currents due to defects associated with ion implantation processes [7, 8]. An alternative approach to tune the work function of a metal gate is by Fermi level pinning through the introduction of extrinsic interface states arising from a buffer layer and subsequent gate electrode alloying. These extrinsic interfacial states cause the effective work function to deviate from the vacuum work function [3, 4]. An attractive aspect of this technology is that an adequate buffer layer allows the integration of inert refractory metals which are thermodynamically stable on an underlying dielectric such as tungsten (W ) and tantalum (Ta). A suitable buffer layer must have high chemical resistance in order to protect the underlying dielectric from chemical etchants, must be consumed to metal al-

2. Device fabrication In order to evaluate the basic electrical performance of the devices, MOS capacitors have been fabricated on p-type silicon substrate with a resistivity of 50 cm. The various oxide thicknesses needed for work function extraction have been achieved by thinning down identically grown thermal oxides of tox = 100 nm in 5% HF solution. This method has been chosen to keep growth conditions and therefore fixed oxide charge levels constant. Optical lithography has been used to define the gate areas of 7.78 × 10−4 cm2 . A 100 nm thick tungsten film has then been deposited on a 1 nm thick AlNx layer using a von Ardenne DC magnetron sputtering tool to form the W/AlN stack. The gate electrodes have been patterned using a lift-off process.

C 2005 Springer Science + Business Media, Inc. 0957–4522 

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Figure 1 Fabrication scheme for the proposed AlNx /W p-type metal gate process.

Figure 2 Capacitance as a function of gate voltage without AlNx (a) and with AlNx (b) before and after PMA at 400 ◦ C and RTA at 950 ◦ C.

High-frequency capacitance-voltage (HFCV) characteristics have been carried out before and after heat treatment at 400 ◦ C in forming gas (10% H2 /N2 ) and subsequent 950 ◦ C rapid thermal annealing (RTA) in an inert ambient of argon, respectively. The proposed fabrication sequence of deposition and alloying is schematically shown in Fig. 1. All measurements of the capacitors have been obtained using an HP4184B precision LCR meter. P-MOSFETs have been fabricated on silicon-oninsulator (SOI) substrates based on the results from the electrical characterization of the MOS-capacitors. The top silicon of the SOI material is tSi = 100 nm with a buried oxide (BOX) of tBOX = 200 nm. Leaving the top silicon of the SOI intrinsic in order to improve channel mobility, the MESA has been optically patterned and etched in an Oxford Instruments Plasma Lab 100 inductively coupled reactive ion etching tool (ICP-RIE). A highly selective process with HBr/O2 chemistry has been used [11]. A Centrotherm diffusion furnace has been employed for the growth of a tox = 8 nm gate oxide. After oxidation, the gate electrode stack of 100 nm W/AlNx was optically patterned and lifted off in acetone and propanol. The source/drain implant has been performed with boron at an energy of 15 keV, followed by rapid thermal dopant activation of 950 ◦ C for 20 seconds to achieve 1e20 ions/cm3 active charges. The devices have a gate length of L g = 2 µm and a width of Wg = 40 µm. 3. Results and discussion High frequency capacitance-voltage curves of a pure W and a stacked W/AlNx gate electrode before and after

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heat treatment are compared in Fig. 2. The high temperature processes with forming gas at 400 ◦ C and inert gas at 950 ◦ C lead to a decisive shift of the flat band voltage in positive direction from Vth = −0.5 V to Vth = 0 V in the case of 100% tungsten in Fig. 2(a). This is indicative of successful interface charge passivation. In the case of W/AlNx in Fig. 2(b), however, a much larger shift in positive direction from Vth = −1 V to Vth = 0.5 V can be observed. This large Vth = 1.5 V can only be partly explained by interface charge passivation. Here, the larger shift can be ascribed to a combination of defect annealing and a change in metal work function due to formation of an alloy. A comparison of the accumulation or oxide capacitances in Fig. 2(b) confirms this interpretation: Before heating, the AlNx acts as an additional dielectric to the SiO2 resulting in a reduced oxide capacitance, whereas after heat treatment the initial dielectric stack of AlNx /SiO2 is reduced to SiO2 and the accumulation capacitance is increased. Calculations of equivalent oxide thicknesses from the oxide capacitances show that the difference, illustrated in Fig. 2(b), corresponds to a thickness of sputtered AlNx of tAlNx = 1 nm. When comparing the CV curves before heat treatment in Fig. 2(a) and (b), it strikes out that the initial flatband voltage of the W/AlNx film is lower than for pure W. This is attributed to a different amount of interface charges at the SiO2 /metal interface due to the buffer layer. Finally, the CV curves before heat treatment are clearly distorted for gate voltages between flat band condition and accumulation due to interface charges. After annealing, this distortion can no longer be observed independent of the buffer layer. Effective annealing by the high temperature steps can therefore be concluded.

have been plotted against oxide thickness for samples with and without buffer layers as shown in Fig. 4. According to Equation 1, the extracted flat band voltages (VFB ) after linear extrapolation to zero oxide thickness (tox = 0 nm) equals the difference in work function between the gate material and silicon substrate f ms . The gate metal work function can then be calculated with the use of the known silicon work function. VFB + ϕms ± Figure 3 Capacitance as a function of gate voltage after heat treatment of pure W and W/AlNx gate Stack.

The HFCV curve of the sample with AlNx buffer layer is compared to that without a buffer layer in Fig. 3 in more detail. For identical oxide thicknesses of tox = 8 nm, a higher flatband voltage is observed for the W/AlNx gate stack. This is again indicative of a change in intrinsic material properties and the presence of extrinsic states as a result of the alloy formation. A change of the metal work function has to be assumed. A series of samples with varying SiO2 thickness has been used to further investigate the metal work functions. For each oxide thickness, the flatband voltage has been extracted after heat treatment from the HFCV measurement. The resultant flat band voltages

Q SS · tox εox

(1)

The extracted work function with AlNx buffer layer is f m = 5.12 eV compared to f m = 4.6 eV achieved for the case without a buffer layer. The metal work function has thus been changed from silicon mid-gap for pure W to p-type material for the W/AlNx alloy. Output and transfer characteristics of a preliminary p-MOSFET fabricated with W/AlNx gate electrode are illustrated in Fig. 5(a) and (b). Both graphs clearly show well behaved MOSFET characteristics. The calculated inverse sub threshold slope (S) at a drain voltage of Vds = 1 V of 118 mV/dec is within the expected range for undoped channels in SOI devices. Higher channel doping would reduces this value towards an ideal 60 mV/dec and furthermore shift the threshold voltage of the p-MOSFET to a desired negative voltage.

Figure 4 Flat band voltage versus oxide thickness without AlNx (a) and with AlNx buffer layer (b).

Figure 5 Output (a) and transfer (b) characteristics of a p-MOS transistor with W/AlNx gate electrode.

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4. Conclusion We have successfully demonstrated the use of an AlNx buffer layer for controlling the work function of tungsten (W) gate electrodes in this work. Extensive analysis of capacitance-voltage curves proves that with the method described, tungsten can be used as a p-type metal gate with a work function of 5.12 eV. Finally, promising electrical characteristics of a p-type MOSFET underscore the viability of the suggested approach with AlNx buffer layers. Acknowledgments This work has been partly supported by the German Bundesministerium f¨ur Bildung und Forschung (bmb + f) under contract number 01 M 3142 A (“KrisMOS”) and by the European Commission under the frame of the Network of Excellence “SINANO” (Silicon-based Nanodevices, IST-506844).

2. C . H U , Semiconductor International (June 1994). 3. Y . - C . Y E O , P . R A N A D E , T . - J . K I N G and C . H U , IEEE Electron Dev. Lett. 23(6) (June 2002). 4. R . W . M U R T O , M . I . G A R N E R , G . A . B R O W N , P . M . Z E I T Z O F F and H . R . H U F F , Solid State Technology (October 2003). 5. H . S . P . W O N G , IBM J. Res. Dev. 46(2/3) (2002) 133–168. 6. T S U - J A E K I N G , VLSI Symposium (December 200). 7. R . L I N , Q . L U , P . R A N A D E , T . - J . K I N G and C . H U , IEEE Electr. Dev. Lett. 23(1) (January 2002). 8. T . A M A D A , N . M A E D A and K . S H I B A H A R A , Mat. Res. Soc. Symp. Proc. 716 (2002). 9. C . S . P A R K , B . J . C H I O and D . L . K W O N G , IEEE Electr. Dev. Lett. 24(5) (May 2003). 10. J . C . Z O L P E R and R . J . S H U L , Solid State Electr. 41(12) (1993) 1947. 11. M . C . L E M M E , T . M O L L E N H A U E R , H . G O T T L O B , W . H E N S C H E L , J . E F A V I , C . W E L C H and H . K U R Z , Microelectr. Engng. 73–74 (2004) 346. 12. S . M A T S U D A , H . Y A M A K A W A , A . A Z U M A and Y . T O Y O S H I M A , Symp. on VLSI Tech. (2001) p. 63. 13. D . K . S C H R O D E R , in “Semiconductor Material and Device Characterization” (John Wiley & Sons, Inc., 1988). 14. E . H . N I C O L L I A N and J . R . B R E W S , in “MOS Physics and Technology” (John Wiley & Sons, Inc., 1982).

References 1. International Technology Roadmap for Semiconductors: 2002 Update, International Sematech, http://public.itrs.net/Files/ 2002Update/2002Update.pdf, 2002.

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Received 15 September 2004 and accepted 8 February 2005

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