Ultrathin decoupled plasma nitridation SiON gate ...

Ultrathin decoupled plasma nitridation SiON gate dielectrics prepared with various rf powers Chan-Yuan Hu, Shih-Chih Chen, Jone F. Chen, Shoou-Jinn Chang, Min-Hong Wang, Vita Yeh, and Jung-Che Chen Citation: Journal of Vacuum Science & Technology B 25, 1298 (2007); doi: 10.1116/1.2756545 View online: http://dx.doi.org/10.1116/1.2756545 View Table of Contents: http://scitation.aip.org/content/avs/journal/jvstb/25/4?ver=pdfcov Published by the AVS: Science & Technology of Materials, Interfaces, and Processing Articles you may be interested in Electrical and structural properties of ultrathin SiON films on Si prepared by plasma nitridation J. Vac. Sci. Technol. B 29, 022201 (2011); 10.1116/1.3556938 Germanium oxynitride gate dielectrics formed by plasma nitridation of ultrathin thermal oxides on Ge(100) Appl. Phys. Lett. 95, 022102 (2009); 10.1063/1.3171938 Interface trap and oxide charge generation under negative bias temperature instability of p -channel metal-oxidesemiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics J. Appl. Phys. 98, 114504 (2005); 10.1063/1.2138372 Plasma-nitrided silicon-rich oxide as an extension to ultrathin nitrided oxide gate dielectrics Appl. Phys. Lett. 86, 172903 (2005); 10.1063/1.1915523 Monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using remote plasma processing: Formation of stacked “ N–O–N ” gate dielectrics J. Vac. Sci. Technol. B 17, 2610 (1999); 10.1116/1.591034

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Ultrathin decoupled plasma nitridation SiON gate dielectrics prepared with various rf powers Chan-Yuan Hu Institute of Microelectronics, Department of Electrical Engineering, and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 70101, Taiwan

Shih-Chih Chen Department of Electronic Engineering, National Yunlin University of Science and Technology, Touliu 640, Taiwan

Jone F. Chena兲 and Shoou-Jinn Changb兲 Institute of Microelectronics, Department of Electrical Engineering, and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 70101, Taiwan

Min-Hong Wang, Vita Yeh, and Jung-Che Chen United Microelectronics Corporation, Tainan Science-Based Industrial Park, Tainan 74145, Taiwan

共Received 14 December 2006; accepted 14 June 2007; published 26 July 2007兲 Decoupled plasma nitridation 共DPN兲 SiON films for short channel complementary metal-oxide-semiconductor 共CMOS兲 devices were prepared with various rf powers. As we increased the SiON deposition power from 200 to 400 W, it was found that gate leakage current increased while gate breakdown voltage decreased. It was also found that the authors can achieve more uniform thickness and nitrogen distributions across the wafers, smaller off-state current, and better Vt rolloff characteristics from the PMOS field-effect transistors 共MOSFETs兲 with 400 W DPN SiON films. Furthermore, it was found that they can achieve larger hot carrier injection 共HCI兲 lifetime and better HCI resistance from the NMOSFETs with 400 W SiON films. However, it was also found that negative bias temperature instability lifetime of the PMOSFETs with 200 W SiON films was longer. © 2007 American Vacuum Society. 关DOI: 10.1116/1.2756545兴

I. INTRODUCTION In order to improve the performance of complementary metal-oxide-semiconductor 共CMOS兲 devices, one needs to aggressively scale down both gate length and gate oxide thickness simultaneously.1 However, it has been shown that gate leakage current increases significantly with reduced gate oxide thickness due to direct tunneling.2 The large leakage current implies large standby power consumption, which is a major concern for various applications. With thin gate oxides, boron in p-type poly-Si gate electrodes can also penetrate into the conduction channel regions in Si substrates easily to degrade intrinsic oxide reliability and reduce carrier mobility.3,4 These two phenomena could both significantly degrade device performance. One possible way to solve these problems is to use high-k materials as the gate dielectrics.5,6 However, it has been shown that high-k materials are unreliable with poor thermal stability. High-k materials are also not compatible with conventional CMOS processing. The other possible way to solve these problems is to use silicon oxynitride 共i.e., SiON兲 as the gate dielectric.7 It has been shown that SiON has a relatively large dielectric constant so that we can achieve a larger equivalent oxide thickness. Compared with SiO2, SiON gate dielectric can also suppress boron penetration more effectively. To use

II. EXPERIMENTS

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Author to whom correspondence should be addressed; electronic mail: [email protected] b兲 Electronic mail: [email protected] 1298

SiON as the gate dielectric, one needs to pay special attention to the nitrogen distribution profile. Ideally, we need a high nitrogen concentration at the poly-Si/dielectric interface to form a diffusion barrier to boron and a low nitrogen concentration at the dielectric/Si-substrate interface to improve device reliability.8 Recently, it has been shown that remote plasma nitridation 共RPN兲 and decoupled plasma nitridation 共DPN兲 on SiO2 can both be used to achieve high quality SiON films with acceptable nitrogen distribution profile.9 However, it was found that these two methods will also result in a large threshold voltage Vt, shift, and transconductance gm degradation. Compared with RPN approach, it has been pointed out that DPN is more scalable and could provide us better cross wafer nitrogen uniformity. Although one can optimize the nitrogen distribution profile by tuning plasma pressure,10 no report on the rf power on the quality of DPN SiON films could be found in the literature to our knowledge. In this study, we report the preparation of DPN SiON films for 90 nm CMOS with various rf powers. We prepared standard NMOS with n+ poly gate and p well while PMOS with p+ polygate and n well. Device performances, including negative bias temperature instability 共NBTI兲 induced degradation and lifetime,11–13 of the NMOS and PMOS with the DPN SiON will also be discussed.

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Devices used in this study were all fabricated on p-type Si 共110兲 substrates using 90 nm CMOS technology. After stan-

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©2007 American Vacuum Society

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dard cleaning process, we first grew thin thermal oxides 共i.e., 1.3 nm兲 on the Si substrates. DPN was then performed using continuous-wave rf N2 plasma with various rf powers for nitrogen incorporation and the formation of SiON films. During DPN, we kept the chamber pressure at 80 mtorr with three rf powers 共i.e. 200, 300, and 400 W兲. Here, 80 mtorr was chosen to reduce collision probability and recombination rate of active nitrogen which might occur at high chamber pressures.14 With these conditions, we should also be able to control the nitrogen diffusion so that peak nitrogen concentration should occur near the interfaces of polysilicon gates and SiON films. It was found that the reactive nitrogen doses were 1.46⫻ 1015, 2.3⫻ 1015, and 2.77⫻ 1015 cm−2 for the gate dielectrics deposited with rf powers of 200, 300, and 400 W, respectively. Postnitridation annealing was then preformed at 1000 ° C in dilute oxygen ambient for stabilization. It was found that the final physical thickness of the SiON films were 1.53, 1.55, and 1.59 nm for the gate dielectrics deposited with rf powers of 200, 300, and 400 W, respectively. The larger final physical thickness observed from the SiON films deposited with larger rf power could also be used to explain the higher nitrogen doses observed in these films. After SiON deposition, we capped the samples with n+ polysilicon gate and p+ polysilicon gate for the fabrication of NMOS and PMOS, respectively. A standard 90 nm CMOS process was used to fabricate both NMOS and PMOS field effect transistors 共MOSFETs兲. NBTI characteristics are important for PMOSFET with thin SiON gate oxide. When a voltage stress was applied onto the thin SiON gate oxide at a different temperature with different duty cycles of stress time, threshold voltage of the PMOSFET shifted due to NBTI. It has been shown previously that NBTI induced degradation is one of the major concerns for ultrathin SiON gate oxide of PMOSFET. Thus, NBTI is of significant concern for CMOS circuits.16,17 In this article, we also studied NBTI lifetime results for the PMOSFET with DPN SiON prepared at various rf powers. III. RESULTS AND DISCUSSION In order to evaluate the performance of SiON layers, we first fabricated NMOSFETs and PMOSFETs with large gate length L 共i.e., 100 ␮m兲 and small gate width W 共i.e., 2 ␮m兲. Figure 1 shows measured gate leakage current densities Jg for such transistors with DPN SiON films prepared at different rf powers. During Jg measurements, 1.2 V stress was applied onto the gate of the transistors while source and drain were grounded. It was found that leakage currents of PMOS were smaller than those observed from NMOS due to the tunneling effect. It was also found that leakage current densities observed from transistors with 400 W DPN SiON films were 30% larger than those observed from transistors with 200 and 300 W DPN SiON films. The larger leakage current densities seem to suggest that interface densities in the transistors with 400 W DPN SiON films were larger. This could be attributed to larger plasma induced damages as a result of increases in plasma power during DPN. It also

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FIG. 1. Measured gate leakage current densities Jg for such transistors with DPN SiON films prepared at different rf powers.

indicated that electrical oxide thicknesses of the transistors with 400 W DPN SiON films were smaller. It should be noted that the leakage current densities shown in Fig. 1 were all reasonably small. In other words, the gate dielectrics fabricated in this study could all be used for practical device applications even for the DPN SiON films deposited at 400 W. We also measured breakdown behaviors from 66 fabricated PMOSFETs and 66 fabricated NMOSFETs. Figures 2共a兲 and 2共b兲 show cumulative breakdown probability as a function of applied bias for the 共W / L兲 = 共80 nm/ 100 ␮m兲 NMOSFETs and PMOSFETs, respectively, with DPN SiON films prepared at different rf powers. Here, we define average breakdown voltage as the applied bias when cumulative breakdown probability equals 0.5. With such definition, it was found that average breakdown voltages were 3.85, 3.82, and 3.79 V for the PMOSFETs with 200, 300, and 400 W DPN SiON films, respectively. It was also found that average breakdown voltages were −3.68, −3.62, and −3.58 V for the NMOSFETs with 200, 300, and 400 W DPN SiON films, respectively. The slightly smaller average breakdown voltages observed from the PMOSFETs and NMOSFETs with 400 W DPN SiON films could be again attributed to the larger plasma induced damages at high plasma power. Figures 3共a兲 and 3共b兲 show the measured capacitancevoltage 共C-V兲 relationship of the fabricated NMOSFETs and PMOSFETs, respectively, with DPN SiON films prepared at different rf powers. In these measurements, we kept 共W / L兲 = 共80 nm/ 100 ␮m兲. From the curves shown in Fig. 3共a兲, it was found that capacitance equivalent thicknesses measured in the inversion region of C-V, CETinv, were 23.7, 23.0, and 22.5 Å while shifts of threshold voltage Vt were 0.238, 0.226, and 0.210 V for the NMOSFETs with 200, 300, and 400 W DPN SiON films, respectively. Although CETinv is within fractions of an angstrom, the Vt is very sensitivity to CETinv due to ultrathin SiON. As we increased the deposition power of DPN SiON films, we increased the nitrogen dose in the based oxide and thus reduced CETinv. On the other hand,

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FIG. 2. Cumulative breakdown probability as a function of applied bias for the 共W / L兲 = 共80 nm/ 100 ␮m兲共a兲 NMOSFETs and 共b兲 PMOSFETs.

the smaller Vt shift observed from the NMOSFETs with DPN SiON films prepared at larger power could be attributed to the smaller CETinv. It was also found that CETinv were 25.7, 24.9, and 24.4 Å while Vt were 0.312, 0.349, and 0.361 V for the PMOSFETs with 200, 300, and 400 W DPN SiON films, respectively. With larger DPN deposition power, we can also achieve relatively more negative flat band voltage Vfb at the accumulation region for PMOSFETs due to the higher nitrogen concentration, reduced boron penetration, and the increased amount of fixed oxide charge Q f and interface trap charge Qit at oxide/substrate interfaces. Thus, the Vt shift became larger as we increased the deposition power of DPN SiON films for PMOSFETs. DPN SiON films were also applied to practical devices with small gate length. For these applications, we fabricated devices with various gate lengths L, while we kept the gate width W at 5 ␮m. Figure 4共a兲 shows measured relationships between on-state saturation current Idsat and off-state current Ioff for such NMOSFETs with DPN SiON films prepared at different rf powers. During these measurements, we kept the drain-source voltage Vds at 1.2 V. It can be seen that Ioff increased as Idsat was increased

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FIG. 3. Measured C-V relationship of the fabricated 共a兲 NMOSFETs and 共b兲 PMOSFETs.

for all three different kinds NMOSFETs. With the same Idsat, it was found that we achieved almost identical Ioff from the NMOSFETs with DPN SiON films prepared at 200, 300, and 400 W. Figure 4共b兲 shows measured relationships between Idsat and Ioff for the PMOSFETs with DPN SiON films prepared at different rf powers. With the same Idsat, it was found that we achieved the smallest Ioff from the PMOSFETs with DPN SiON films prepared at 400 W. Compared to the PMOSFETs with 200 W DPN SiON films, it was found that we can reduce the off-state current Ioff by a factor of 7 from the PMOSFETs with 400 W DPN SiON films when Idsat = 270 ␮A / ␮m. In other words, we can achieve larger Idsat with the same Ioff using the 400 W DPN SiON films. This could be attributed to the fact that more nitrogen atoms were incorporated into the gate dielectrics deposited at 400 W so that much less boron in the p+ polysilicon gate could penetrate into the channel regions of the PMOSFETs. As a result, we can achieve smaller subthreshold leakage. Figures 5共a兲 and 5共b兲 show measured drain current Id in log scale as a function gate voltage Vg for the fabricated NMOSFETs and PMOSFETs, respectively. We can calculate the subthreshold swing 共St兲 from these curves. Here, St is defined as

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FIG. 4. Measured relationships between on-state saturation current Idsat and off-state current Ioff for the 共a兲 NMOSFETs and 共b兲 PMOSFETs with small gate length.

FIG. 5. Measured drain current Id in log scale as a function gate voltage Vg for the fabricated 共a兲 NMOSFETs and 共b兲 PMOSFETs.

log共d ln Id / dVg兲−1. From Fig. 5共a兲, it was found that St of the NMOSFETs with DPN SiON films prepared at 200, 300, and 400 W were 77.3, 76.5, and 77.6 mV/ dBm, respectively. On the other hand, we found from Fig. 5共b兲 that St of the PMOSFETs with DPN SiON films prepared at 200, 300, and 400 W were 78.8, 77.2, and 78.2 mV/ dBm, respectively. From these values, we concluded that subthreshold swing of the fabricated devices is almost independent of the rf power used during the deposition of DPN SiON films. It should be noted that the PMOSFET with 400 W DPN SiON film exhibits the lowest subthreshold leakage, as shown in Fig. 5共b兲. Such a result agrees well with the fact that more nitrogen incorporation and distributed at the interface between p+ poly and SiON could effectively suppress boron penetration from p+ poly.10 On the other hand, the highest leakage current observed from 400 W DPN SiON films should be attributed to the larger plasma induced damages, as shown in Fig. 1.

Short channel effects of the fabricated devices were also investigated. Figures 6共a兲 and 6共b兲 show Vt rolloff plots of NMOSFETs and PMOSFETs, respectively, with DPN SiON films prepared at different rf powers. It can be seen that similar Vt rolloff behavior was observed from the NMOSFETs prepared at different rf powers. For PMOSFETs, however, it was found that Vt rolloff characteristics of the devices with 400 W SiON films seem to be better than those with 200 and 300 W SiON films. Figures 7共a兲 and 7共b兲 show measured substrate current Isub as a function of on-state saturation current Idsat for the fabricated NMOSFETs and PMOSFETs, respectively. With the same Idsat, it was found that we achieved the lowest Isub from NMOSFETs with 400 W SiON films, as shown in Fig. 7共a兲. Previously, it has been shown that the lifetime of hot carrier injection 共HCI兲 is proportional to 共Isub / Idsat兲−n, where n is a constant.15 With smaller Isub / Idsat, we should be able to achieve larger HCI lifetime and thus better HCI resistance from the NMOSFETs with 400 W SiON films. On the other hand, such phenomenon

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FIG. 6. Vt rolloff plots of 共a兲 NMOSFETs and 共b兲 PMOSFETs with DPN SiON films prepared at different rf powers.

FIG. 7. Measured substrate current Isub as a function of on-state saturation current Idsat for the fabricated 共a兲 NMOSFETs and 共b兲 PMOSFETs.

was not observed in PMOSFETs. As shown in Fig. 7共b兲, it was found that Isub was almost independent of the rf power. Since NBTI induced degradation is one of the major concerns for ultrathin SiON gate oxide of PMOSFET, we also evaluated NBTI characteristics of the fabricated PMOSFETs with W = 5 ␮m and L = 0.08 ␮m. During NBTI measurements, we applied various gate bias stressing voltages 共i.e., Vg = −1.5, −1.7, and −1.9 V兲 onto the devices at 125 ° C. Threshold voltage shift ⌬Vt was then measured as a function of stress time. Figures 8共a兲–8共c兲 show such a relationship for the PMOSFETs with DPN SiON films deposited at 200, 300, and 400 W, respectively. With the same stressing voltage, it was found that threshold voltage shift ⌬Vt increased for all three samples as we increased the stressing time. Similarly, it was found that ⌬Vt became larger as we increased the gate bias stressing voltage for these samples with the same stressing time. During NBTI stressing, holes in the inversion layer might gain sufficient energy to dissociate the Si–H bonds in the SiON films. This will result in the generation of interface

states and fixed oxide charges. The dissociated hydrogen atoms will then diffuse toward p+ polygate electrode to result in threshold voltage shift. Such an effect will be enhanced as we increase the stressing voltage and the stressing time. Using the reaction-diffusion model, we found that threshold voltage shift ⌬Vt shown in these figures can be fitted well by ⌬Vt = ␣ ⫻ t␤, where ␣ and ␤ are two constants and t is the stressing time. It should be noted that the constants ␣ and ␤ depend on the stressing voltage, operation temperature, and activation energy Ea of the process that generates interface states and/or fixed oxide charges.16,17 From the NBTI data shown in Figs. 8共a兲–8共c兲, it was found that the exponential constant ␤ were 0.232, 0.243, and 0.253 for the PMOSFETs with DPN SiON films deposited at 200, 300, and 400 W, respectively. Previously, it has been shown that surface state density increases as t1/4 after negative bias stress for MOS devices.17 Thus, we believe that the threshold voltage shift observed from our devices is dominated by the increased surface state density. Here, we define the lifetime of NBTI by extrapolating the data shown in Figs. 8共a兲–8共c兲 to stressing



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FIG. 9. Lifetime of NBTI by extrapolating the data shown in Figs. 8共a兲–8共c兲 to stressing voltage Vg = 1.32 V.

that lifetimes of the PMOSFETs deposited with 200, 300, and 400 W DPN SiON films were all larger than ten years. IV. CONCLUSION In summary, DPN SiON films for 90 nm CMOS were prepared with various rf powers. It was found that gate leakage current increased while gate breakdown voltage decreased as we increased the SiON deposition power from 200 to 400 W. It was also found that we can achieve more uniform thickness and nitrogen distributions across the wafers, smaller off-state current, and better Vt rolloff characteristics from the PMOSFETs with 400 W DPN SiON films. Furthermore, it was found that we can achieve larger HCI lifetime and better HCI resistance from the NMOSFETs with 400 W SiON films. Although the PMOSFETs with 200 W SiON film were more reliable, lifetime of the PMOSFETs deposited with 400 W DPN SiON film was still larger than ten years. ACKNOWLEDGMENTS FIG. 8. Threshold voltage shift as a function of NBTI stress time for the PMOSFETs with DPN SiON films deposited at 共a兲 200, 共b兲 300, and 共c兲 400 W.

The authors would like to thank the entire gate dielectric processing line of UMC for the support of this work. J. Gautier, Microelectron. Eng. 36, 3 共1997兲. H. S. Momose, S. I. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, IEEE Trans. Electron Devices 45, 691 共1998兲. 3 Z. J. Ma, J. C. Chen, Z. H. Liu, J. T. Krick, Y. C. Cheng, C. Hu, and P. K. Ko, IEEE Electron Device Lett. 15, 109 共1994兲. 4 Y. Okazaki, S. Nakayama, M. Muyake, and T. Kobayashi, IEEE Trans. Electron Devices 41, 2369 共1994兲. 5 J. S. Lee, S. C. Sun, S. J. Chang, J. F. Chen, C. H. Liu, and U. H. Liaw, Jpn. J. Appl. Phys., Part 1 41, 690 共2002兲. 6 G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, IEEE Trans. Device Mater. Reliab. 5, 5 共2005兲. 7 C. H. Lai, B. C. Lin, K. M. Chang, K. Y. Hsieh, and Y. L. Lai, Jpn. J. Appl. Phys., Part 1 45, 4898 共2006兲. 8 M. Okushima and K. Noguchi, Jpn. J. Appl. Phys., Part 1 39, 2035 1 2

voltage Vg = 1.32 V. As shown in Fig. 9, it was found that we can achieve a longer lifetime by reducing the rf power of the DPN SiON films during deposition. This could be attributed to the smaller interface trap and fixed oxide charge density and thus smaller threshold voltage shift ⌬Vt for the device fabricated with lower rf power for DPN SiON films. Such a result also agrees well with the observation shown in Fig. 3共b兲 that Vt shifts with increased rf power. It should be noted JVST B - Microelectronics and Nanometer Structures


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共2000兲. C. H. Chen et al., IEEE Trans. Electron Devices 49, 840 共2002兲. 10 H. H. Tseng et al., IEEE Electron Device Lett. 23, 704 共2002兲. 11 G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, IEEE Electron Device Lett. 23, 734 共2002兲. 12 V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, Microelectron. Reliab. 45, 31 共2005兲. 9

1304 S. Y. Chen et al., Jpn. J. Appl. Phys., Part 1 45, 3266 共2006兲. M. L. Green et al., Appl. Phys. Lett. 65, 848 共1994兲. 15 A. Ito, IEEE Trans. Electron Devices 40, 1347 共1993兲. 16 C. Y. Chen, J. W. Lee, W. C. Chen, H. Y. Lin, K. L. Yeh, P. H. Lee, S. D. Wang, and T. F. Lei, IEEE Electron Device Lett. 27, 893 共2006兲. 17 A. K. O. Jeppson and C. M. Svensson, J. Appl. Phys. 48, 2004 共1977兲. 13 14

