Vector Quantization Model - IEEE Xplore

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In this paper a novel image coding scheme, based on coinbination of fractal and ... processing, such as image segmentation, image analysis, ... DSP 97 - 797 ...
IMAGE CODING USING A FRACTALWECTOR QUANTIZATION MODEL K. Masselos, G. Kittes, Y. A. Karayiannis, and T. Stouraitis Department of Electrical and Computer Engineering University of Patras, Rio 261 10, Greece tel: (+) 30 61 997323 fax: (+) 30 61 994798 email: [email protected] ABSTRACT In this paper a novel image coding scheme, based on coinbination of fractal and vector quantization techniques is proposed. A two-level coding scheme is described. In the first level, a form of vector quantization is employed to get a rough first-order approximation of the image. In the second level, the residual image, produced after subtracting thc first-order approximation limn the original image, is coded using a simple, fixed-block size fractal technique. Using fixed block size, the algorithm has a very simple and regular structure. The benefit of the proposed technique is the reduction of' the computational complexity in comparison to traditional fractal coding, while the image quality is kept i n high levels

1. INTRODUCTION Fractal block coding is a novel technique for lossy compression of natural images. Fractal-based techniques have been employed in several areas of digital image processing, such as image segmentation, image analysis, image synthesis, computcr graphics, and texture analysis. Barnsley [ 1,2] first proposed the use of fractals for image compression. In hi5 method, the image is divided into non-overlapping parts. Each part is considered a contractive mapping of another larger one and it is represented by the parameters of this mapping. Compression ratios of up to 10000:I can be achieved. The basic disadvantage of this approach is the large computational effort required i n order to divide the image into parts and to find the best mapping for each part.

where Rk is the k-dimensional space, C is the codebook of N k-dimensional words yi and d is the distortion criterion used. A vector, which is a block of pixels, is approximated by a representative vector (codeword) of the codebook, which minimizes the distortion among all the vcctors in the codebook. Compression i s achieved by transmitting or storing the codeword address instead of the codeword itself. In this paper, the image coding is performed in two levels: In the first level, the image is divided into large regions, which are coded using Hierarchical Vector Quantization [6]. The residual image, produced hy removing the first-order approximation from the original, is coded using a simple fixed block size fractal scheme.

Jacquin [3,4] presented a simpler and more practical fractal coding technique. In his approach the image is divided into non-overlapping squarc blocks, called range blocks, which are ified by their space complexity. The low-complexity rangc blocks are approximated by their mean value, while the morc complex blocks are approximated by other image blocks, bigger in size, called domain blocks, after applying on them certain transformations. If the approximation error is large, the original range block is divided into four sub-blocks and the same search for a better approximation is performed in each one of these four sub-blocks. This partition is known as quad-tree image partition. Each image block is represented in the image's coded form by the index of tlic selected domain block and the transformation paramctcrs. The large computational cost is, again, the main drawback 0 1 the algorithm. Fisher 151 proposed M similar quad-trec technique for fractal imagc coding. The image is divided into non-ovcrlapping 16x16 pixel range blocks. The smallest possible range block size is 4x4. Computational complexity remains high. Vector Quantization (VQ) 161 is an efficient imagc coding technique achieving low bit ratcs i.c. lower than I bit per pixel. Vector quantization is described by the following equation:

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The rest of the paper is organized as follows: Section 2 describes the proposed algorithm, while i n section 3 experimental results are presented. In section 4, an architecture for implementing the algorithm in hardware is proposed. Finally, conclusions are presented in section 5.

2. PROPOSED ALGORITHM The proposed algorithm is based on a combination o l fractal coding and the Mean-Removed Vector Quantization (MRVQ), a variation of the Hierarchical Vector Quantization (HVQ) [ 6 ] . The Hierarchical Vector Quantization extracts from the supervector (the original image) a feature vector of reduccd dimensionality, which describes attributes of the supervector that account for much of the correlation or inter-dependence among its pixels. The feature vector can be coded with a suitable vector quantization technique and the quantized feature vector, either by

-

797

itself or in combination with other information, can generate an approximate description of the supervector. The Mean-Removed Vector Quantization, splits the original vector into two vectors, the mean-vector that represents a general background level and the residual vector that represents the shape of the vector about its mean. The proposed coding scheme divides the original image into large fixed size regions from which the mean value is extracted. This way, the main part of the correlated information of the image is captured in the mean image that is coded using HVQ while the edges and the complex regions are preserved in the residual image that is coded in the second level.

for all i j E {0...B-11, where I(i)=ic,+2i and J(j)=jt,+2j

2) Contrust Scaling: This transformation multiplies the pixels of a shrunk domain block by a constant factor U . 3) Lzrm~nunce~ h d tIt adds a constant value A, to eveiy pixel of the shrunk domain block. 41 Isomelries: The isometries simply shuffle the pixels of the shrunk domain block without affecting their values. There are eight canonical isometries [ I ] for a square block of size BxB.

Using fractal coding at the second level, edges and complex regions are well-approximated [3,4]. There is no need to use complicated fractal coding schemes due to the significant part of the initial information of the image that has already been removed at the first level of coding.

The first transformation is the geometric part of the transformations applied to the domain blocks, while the other three constitute the mastic part of the transformations applied on the domain blocks and affect their pixel values.

A technique similar to the one proposed by Jacquin in [3,4] is used for the fractal coding of the residual image. The main differences from the technique proposed by Jacquin are the following:

The parameters U and A, of contrast scaling and luminance shift respectively are computed in the following way: Given two blocks of BxB pixels with (range pixel values dlj (shrunk domain block) and

a)

block), a scaling factor U and a luminance shift A, can be found to minimize the square error

Only non-overlapping domain blocks are considered. This way, the computational complexity is reduced. b) Classification is not applied on the range blocks. c) The image is divided into fixed size range blocks (no quad-tree partitioning is performed).

cl

B

E = c ( u x dl, + A s - rj,)* . The minimum E occui-s i,j=l

when the partial derivatives, with respect to U and Ag, are zero [8]. Then (I and A, are given by the following equations:

The absence of classification and quad-tree partitioning lead to increased regularity, compared to classical fractal coding techniques [ 1,3,4,5], which is very important as far as hardware implementations are concerned. The residual image is di\iided into non-overlapping range blocks of size BxB pixels. These range blocks are coded independently. The image is also divided into non-overlapping domain blocks of fixed size 2Bx2B. The goal of the coding procedure i s to find for each range block the domain block, which, after certain transformations, best approximates the original block, in terms of a specific distortion criterion. The possible transformations are the following: I ) Shrinking: This transformation affects the size of the block. It averages the pixel values of the domain block and then subsainples it by 2 in both spatial dimensions. In this way, each doinain block becomes equal to the range blocks. Let a domain block D (id, j,) of size 2B X ZB, and a range block R(ir, j,) of size B X B , where

(id, j,) and (i,., j,) are the indices of the top left corner of the two blocks respectively. The domain block is mapped to the range block through the equation:

The massic transformations described above allow the

generation of eight geometrically related transformed shrunk domain blocks which are considered as candidate matching blocks during coding. Each range block of the residual image is represented i n the code-file by the index of the selected domain block and by the transformation coefficients that minimize the distortion criterion. This information can be used to recreate the residual image. As far as the residual image is concerned, the decoding procedure i s a typical fractal decoding one. Starting from an arbitrary image, of the same size as the original (residual), for each range block, the transformations described in the code-file are iteratively applied on the domain block selected during

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the coding. After a number of iterations, the range blocks converge to their final pixel values. Adding the decoded residual image to the decoded mean image, where the pixel values of each region are replaced by the mean value of the region, produces the final decoded image. The comparison of a range block of size (Bx5) pixels with a candidate matching block requires (4 B 2 + 9) multiplications, (9 B2 - 8) additions, ( B2 + 3) subtractions and 1 division (the computation required for shrinking the domain blocks is not included, since it is performed only once). Using isometries, eight candidate domain blocks are produced from a single domain block. Assuming that the above computation takes time t, the number of range blocks is R and the number of domain blocks is D , then the time T, required to encode the whole image equals:

T=RxDx8x

1

This estimated time is valid for block sequential encoding on a single processor.

3. EXPERIMENTAL RESULTS The proposed coding algorithm was applied to the test images “Lena” and “Man” of size 256x256 pixels and quantized to 256 gray levels. The coding results for various range block sizes are shown in table 1. It must be noted that the mean values of HVQ regions were scalar-quantized using 6 bits. It is straightforward that as the block size increases, the quality of the output image is degraded. However, this degradation of the quality is smaller than the one corresponding to when fractal and vector quantization schemes use the same block size [ 3 ] . The outputs of the proposed algorithm for test images Lena and Man for block size 4x4 are shown in figure 1.

Table 1 : Experimental results

4. PROPOSED ARCHITECTURE The basic disadvantage of fractal coding is the computational complexity. Real-time fractal coding can only be performed in parallcl processing [7] structures. An architecture for real-time fractal video coding is described in [SI. This architecture employs a systolic array [9] to perform fixed-block-size full-search fractal coding. The computation of the fractal code for the residual image dominates the total computation budget of the proposed algorithm. A parallel architecture is proposed

for the coding of the residual image. This architecture exploits the inherent data parallelism of fractal coding, i.e. the fact that each range block can be coded independently. Speed can be increased significantly i l range blocks are coded in parallel. However, the amount of parallelism depends highly on the amount of the available hardware. An important point as far as the proposed architecture is concerned is the increased regularity, because of the fixed size of range blocks. Quad-tree partitioning and block classification used by other fractal coding techniques lead to complex control and to irregular flow of &main blocks from memory to processing units. The regularity of the proposed algorithm leads to very simple control and regular now of domain blocks through a parallel array of identical processing elements. The proposed architecture is shown in fig. 2. The subsampled by 2 in both spatial directions residual image is stored in the domain pool memory. Assuming that an image of NxN pixels will be coded and the size of range blocks is BxB while the size of the domain

N xN range blocks blocks is 2Bx2B then there are B B N 2B

N 2B

blocks. Each domain block is

and -x-domain

initially fed to a circuit implementing the 8 isometrics. This way, 8 geometrically related domain blocks are generated from a single one and the real number of candidate matching blocks for each range block

N 2B

becomes 8 x - x - .

N 2B

Then each domain block is

passed to the one-dimensional processing array and in a pipelined fashion from each processing element to its neighbor-processing element. Each processing element is responsible for the coding of a range block and consists of two parts. The first part stores temporarily the domain block under matching and permanently the range block under coding. It accumulates pixels and produces the sums of products required in equations 3 and 4 for the computation of the contrast scaling factor a and the luminance shift Ag. Thus, the first part of the processing element consists of a memory block and a MAC unit. The second part of the processing element computes the transformation parameters and the distortion between transformed domain blocks and range blocks. This part consists of adder, multiplier, divider and RAM for temporary values and running minimum match values. Let the number of available processing elements is

N x -, N i.e. . equal to the number of the range blocks, B B

-

and assume that the time required to perform the matching procedure between a range block and a candidate block is 1. Then, the time required by thc proposed architecture for the coding of the whole image

N 2B

N 2B

isSx-x-xt+

The time required by a single processor would be

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N

N

N

N

2B

2B

B

B

8x-X-X-x-xt

for coding the whole

image. Thus, the parallel-processing array increases the

($1.

speed of the coding procedure by a factor of

5 . CONCLUSIONS

An image coding scheme, based on fractal coding and hierarchical vector quantization, was presented in this paper. The image is divided into large areas, from which the mean value is extracted. This way, a first-order rough approximation of the image is obtained. The residual image, representing the shapes of image regions around their mean values, is coded using a simple fixed block size fractal-coding scheme. The image quality is kept high in terms of SNR. Furthermore, using a fixed block size, the proposed technique enables simple and regular hardware implementations of the algorithm in parallel processing arrays with very regular dataflow and no complex control. Such parallel implementations allow execution of fractal coding in real-time.

REFERENCES

121 M. F. Barnsley, Fractals Everywhere, New York: Academic Press, 1988. [3] A. E. Jacquin, “Image Coding Based on Fractal Theory of Iterative Contractive Image Transformations”, IEEE Trans. on Image Processing, Vol. 1, January 1992. [4] A. E. Jacquin “Fractal Image Coding: A Review”, Proceedings of the IEEE, V0l.8 I , pp. 1451- 1464, No. I O , October 1993. [5] Yuval -Fisher, Fractal Image Compression, SpringerVerlag, New York, 1995. [6] R. N. Gray and A. Gersho “Vector Quantization and Signal Compression”, Kluwer Academic Publishcrs 1992.

[7] D. A. Paterson, J . L. Henessy, “Compuier Architecture: A Quantitative Approach”, Morgan Kaufmann Publishers Inc., 1990. [SI Z. He, M. Liou, K. Fu, “VLSI Architecture for Real Time Fractal Video Encoding”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 1996, pp. 738-741. [9] S. Y. Kung, VLSI Array Processors, Prentice Hall, 1988.

[I] M. F. Barnsley, Fractal Image Compression, A. K. Peters, 1994.

Figurc I : Output of the proposed algorithm for images Lena and Man, respectively, and block size 4x4 Piocessing element

Domain blocks

-

Parallel processing array Figure 2: Proposed architecture.

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