Vertex Detector Electronics - L1 Electronics Prototyping LHCb

Vertex Detector Electronics L1 Electronics Prototyping

LHCb Technical Note Issue: Revision:

1 1.0

Reference: Created: Last modified:

LHCb 98-069 TRAC 20 October 1998 13 February 1999

Prepared By:

Yuri Ermoline

Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note Abstract

Ref: LHCb 98-069 TRAC Issue: 1 Revision: 1.0 Date: 13 February 1999

Abstract This paper discusses a proposal for the prototyping of the vertex detector off-detector electronics (ODE, or L1 electronics).

Document Status Sheet Table 1 Document Status Sheet 1. Document Title: Vertex Detector Electronics - L1 Electronics Prototyping 2. Document Reference Number: LHCb 98-069 TRAC 3. Issue

page ii

4. Revision

5. Date

6. Reason for change

Draft

0.1

20 October 98

First version

Draft

0.2

30 October 98

Comments from A.Bay

Draft

0.3

6 November 98

Discussions on L1 trigger interface

1

1.0

13 February 99

Final version with proof-reading by D.Steele

Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note Table of Contents


Table of Contents 1 Introduction

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2.1 Functionality . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Implementation . . . . . . . . . . . . . . . . . . . . . . 8

3 Other prototypes functionality

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3.1 L1 vertex trigger interface (Vertex Trigger Preprocessor) 3.2 L1 buffer and DAQ interface . . . . . . . . . .

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Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note Glossary


Glossary ASIC

Application Specific Integrated Circuit - a custom made integrated circuit

BxID

Bunch crossing (x) IDentification number

DAQ

Data AcQuisition system

DCS

Detector Control System

DPM

Dual Port Memory

DSP

Digital Signal Processor

EvID

Event IDentification number

FADC

Flash Analog to Digital Converter

FEE

Front-End Electronics (L0 Electronics *)

FPGA

Field Programmable Gate Array

HDL

Hardware Description Language - used for ASIC and FPGA design (e.g. are VHDL and Verilog)

I2C

Inter-IC Control bus, a two-wire bus for providing a communication link between integrated circuits from Philips Semiconductors.

JTAG

Joint Test Action Group, IEEE Std. 1149.1_1190 describing the Test Access Port (4-pins serial port) and Boundary Scan Architecture.

ODE

Off-Detector Electronics (L1 Electronics *)

TTD

Timing and Trigger Distribution (TFC - Trigger and Fast Control *) system

TTC

Timing, Trigger and Control distribution system by optical fibres (RD12)

* Synonym to the term

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Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note 1 Introduction


1 Introduction The vertex detector read-out electronics follows an architecture described in the LHCb Technical Proposal [1] and ideas discussed in LHCb notes [2], [3]. The general functional diagram is shown on Figure 2 and consists of Front-End Electronics (FEE, or L0 electronics) and Off-Detector Electronics (ODE, or L1 electronics). The vertex detector is divided in stations. Each station has 2 planes of silicon detectors (with circular and radial strips) divided into sectors. Each sector is further subdivided in zones with different strip pitches. Front-end electronics 128-channel front-end chips perform analog data storage during L0 latency and transmission to the L1 electronics after receiving a L0 accept via analog data links (4 link per FE chip). The TTC receiver chip provides the reset, clock and L0 Accept signals to the front-end chips. The I2C serial bus is used to control/monitor both the front-end chips and the TTC receiver chip via the Detector Control System (DCS) interface. The event from the front-end chip consists of a distributed over 4 links pseudo-digital event header followed by analog data samples. A proposed front-end chip output data format is shown below:

Link 1 1 2 3 4

33 34

PID[0] PID[4] Ch 0 Ch 1

Ch 30 Ch 31

Link 2 PID[1] PID[5] Ch 32 Ch 33

Ch 62 Ch 63


Ch 94 Ch 95


Pseudo-digital header

“HIGH” = ‘1’ “LOW” = ‘0’

Analog samples

“HIGH” = ‘11111111’ “LOW” = ‘00000000’

Ch 126 Ch 127 Idle state(s)

FE chip data

Figure 1. Off-detector electronics A L1 electronics performs analog data digitizing, synchronization tasks (as discussed in [2] using signals from the TTC receiver chip), data preprocessing for the L1 vertex topology trigger, digital data storage during L1 latency, data processing by digital signal processors (DSPs) after L1 Accept and transmission to the data acquisition system (DAQ).

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128 input channels

Front-End Electronics (FEE)

Control logic

TTC receiver

Front-End chip

Control interface (I2C-bus)

Clock 40MHz L0 Accept 1MHz Reset

Analog pipeline (128 cells)

DCS interface

Derandomiser (8/16 cells) Analog MUX 34:1 @ 40MHz

PID + analog samples FE chip data DCS Link

Analog Data Links (twisted pairs)

TTC Link (optical)

FE emulator

L1Buffer data

L1 Buffer

L1 decision

Synchronization logic

Vertex Trigger Interface

FADC

Delay

TTC receiver

Vertex Trigger Preprocessor

Off-Detector Electronics (ODE)

VTP data VTI data

L1 Accept 40 kHz

L1 decision logic

input interface Processing (DSP) FE MUX data

Control interface

Control/Monitoring Link (CAN-bus ?)

output interface

DAQ interface (Front-End Multiplexer)

FE Link (to RU)

Figure 2.

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VT Link data

FE Link data

VT Link (to L1 trigger)



Off-detector electronics partitioning The necessary functionality of the L1 electronics may be implemented in different ways and allows different partitioning, layout and interconnections. One possible partitioning of the L1 electronics inside a read-out crate is shown on Figure 3: •

Read-Out Modules and DAQ interface (a front-end multiplexer),

•

Vertex Trigger Preprocessors and Vertex Trigger Interface,

•

A Control Interface module.

Vertex Trigger interface


Read-Out Module


Read-Out Module

DAQ interface (Front-End Multiplexer)

Control interface


Control

Trigger data path DAQ data path Read-Out crate (One VD station) (DCS i/f)

FE Link (to RU)

VT Link (to L1 trigger)

Figure 3. The Read-Out Module (dash line on Figure 2) may be a “standard” board for sub-detectors with the same L0 electronics (e.g. inner tracker and RICH with pad read-out option). The Vertex Trigger Preprocessor is specific for the vertex detector. A task of the DAQ interface and the Vertex Trigger Interface modules is to collect DAQ or L1 trigger related data from the Read-Out Modules (DAQ) or the Vertex Trigger Preprocessors (L1 trigger) via corresponding DAQ or trigger data paths and send them further.

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Read-Out Module


Read-Out Module

Control interface

Read-Out crate (One VD station)

Control

VT Link (to L1 trigger) (DCS i/f)

FE Link (to RU)

Figure 4. The layout of the read-out crate in a case of direct links from the Read-Out Modules to the DAQ system and from the Vertex Trigger Preprocessors to the L1 trigger system is shown on Figure 4. Off-detector electronics functional prototyping The functional prototyping stage for a limited number of channels is necessary to understand a complexity of different parts, to check new ideas and to define a possible further implementation. The partitioning of the L1 electronics for the prototyping purposes is not necessarily the one chosen for the final implementation. A possible division of the L1 electronics for functional prototyping could be as follows: •

An interface to the L0 electronics. This includes analog line receivers, FADCs with a programmable clock phase adjustment, interface to the TTC system, front-end emulator and synchronization logic as discussed in [2].

•

A L1 buffer with a L1 decision logic and processing after L1 Accept. Data multiplexing and interfacing to the DAQ system may be considered as a common area for L1 electronics and DAQ groups.

•

An interface to the L1 vertex topology trigger - vertex trigger preprocessor.

This division allows us to work on different parts independently implementing them as individual modules.

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Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note 2 L0-L1 interface prototype


2 L0-L1 interface prototype The prototype of the interface to the L0 electronics will be designed to match the final implementation LHCb read-out chip. As an intermediate step, this prototype may be adapted for other read-out chips (e.g. SCTA128). The prototype functionality will be developed gradually using re-programmable logic (FPGAs). Prototypes of the other parts of the L1 electronics are also foreseen.

2.1 Functionality The prototype (Figure 5) performs input analog data digitizing and synchronization tasks and provides data to a L1 buffer and L1 trigger interface prototypes via defined interfaces. A local data storage on the module allows its usage in a stand-alone mode. The number of inputs is limited to 8 which corresponds to 256 detector channels. This is sufficient for synchronisation logic prototyping and supplies enough data for the further data processing after the L1 decision and for the L1 trigger data preprocessing. An interface to the L1 processing DSP may be provided.

TTC Link (optical)

TTC receiver


FADC

Delay FE emulator

L1 decision logic

Synchronization logic

L1B

L1 decision

FE chip data

VTP data

L1T L1Buffer data

Figure 5.

Digitizing and FADC clock phase adjustment The differential line receiver for input analog line (twisted pair) is followed by 8-bit 40 MHz FADC. A 40 MHz clock is provided by the TTC receiver chip. During the prototyping stage an individual (per FADC) programmable delay is provided for the FADC clock phase adjustment. In the final design one programmable delay may be used for a group of FADCs (e.g. - 4 FADCs for the input analog links from one front-end chip).

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TTC interface The TTC receiver [5] provides 40.08 MHz clock and fast control signals for the prototype. The L0 accept signal is derived from channel A of the TTC system. All other control signals (like resets, L1 decision, etc.) are derived from channel B. Front-end emulator The front-end emulator predicts the arrival time of the beginning of the analog samples block in the input analog data stream from the front-end chip and generates a “valid” signal during two first time slots (Figure 1) used for the pseudo-digital header. It also generates a predicted L0 PID (pipeline identification number) for error detection purposes. The front-end emulator receives the same fast control signals as the real front-end chip - reset, clock, L0-accept, it may be set to the same modes of operation and must have the same timing parameters as the real front-end chip. It needs the value of the propagation delay between L0 and L1 electronics which is loaded in internal register via DCS. Event tagging logic The TTC receiver chip may provide the BxID and the EvID but it takes 3 time slots to output them. This may be not acceptable in a case of consecutive L0 accepts. As a solution, only the 12-bits BxID may be used directly from the TTC receiver chip and the EvID may be generated outside of the TTC receiver chip - up to the necessary number of bits. Synchronization logic The synchronisation logic works on the data from 4 input links. It separates individual events using the arrival time prediction from the front-end emulator, generates pseudo-digital data out of analog data, compares the L0 PID with the L1 PID generated by the front-end emulator and sets the error flag for the L1 buffer and masks the event data for the L1 trigger interface in the case of a synchronisation error. The synchronisation logic in the Read-Out Module provides data for the L1 trigger interface and for the L1 buffer with corresponding event identification information (only 16-bit EvID for the L1 trigger and full event tagging - EvID, BxID, PID, error flags - for the L1 buffer). Output to the Vertex Trigger Preprocessor The output to the Vertex Trigger Preprocessor from the synchronisation logic (for 4 input links) consists of four data streams, one per input data link - 32 8-bit words (digitized analog data from the input link) plus event identification number (EvID, 2 8-bit words). The synchronisation logic also provides a control signal indicating the beginning of the 32 word data block (e.g. Figure 6).

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Link N 1 2 3 4

8 1 1 0 0

7

0 L0 EvID_L L0 EvID_H Data 0 Data 1

Event IDentification number

Digitized analog samples 33 34

0 0 0

Data 30 Data 31 00000000

Idle state(s)

VTP data

Figure 6. Therefore, for 8 input links there are 64 output data lines plus 1-2 control lines. The EvID may be one 32-bit word for the data from 4 links. Output to the L1 buffer The output to the L1 buffer from the synchronisation logic (for 4 input links) is a a block of 32-bit words per event (Figure 7) with a full event tagging - EvID, BxID, PID, error flags.

Link 1 1 2 3 4

33 34

Link 2

Link 3

Link 4

00 24-bit EvID Error flags 8-bit PID 12-bit BxID Data 0 Data 32 Data 64 Data 96 Data 1 Data 33 Data 65 Data 97

Data 30 Data 31

Data 62 Data 63

Data 94 Data 95

Data 126 Data 127

L1Buffer data

Figure 7.

Control/monitoring interface A simple control/monitoring interface is provided to access internal registers and memories.

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2.2 Implementation

FE emulator

FADC

FADC

Synchronisation logic Interface logic

I2C-bus I2C-bus controller

VME interface

Control logic

L1T

Event tagging logic

4 x 8-bit data

L1B

Clocks

FADC

FADC

4 x 8-bit data

DAQ

TTC receiver

Clocks

FADC

4

FADC

Clock delay

FADC

4 FADC

Clock delay

FPGA

TTC

The L0-L1 interface prototype will be implemented on a 6U VME board. VMEbus serves as a control/monitoring interface to internal registers/memories (32-bit data/24-bit address). Analog part of the prototype (receivers and FADCs) are implemented on a separate daughter card(s). An individual programmable clock delay for each FADC is implemented on the main VME board.

Local memory

Figure 8. Outputs to the L1 trigger interface and L1 buffer/DAQ interface prototypes are available via connectors (on the front panel or on the board). The local memory on the main VME board may be used for test purposes and as a data storage in a stand-alone mode. Clock delay The digital delay chip [4] from the CERN microelectronics group may be used. It provides 4 independent delay channels with 1 ns step programmed via I2C interface. As an alternative, a programmable delay line may be used at the beginning. TTC receiver The TTC receiver chip (TTCrx [5]) from RD-12 is used. It is mounted on the TTCrx test board which contains the chip itself and other necessary components.

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I2C-bus controller The PCF8584 I2C-bus controller from Philips Semiconductor [6] may be used to drive digital delay chips and TTC receiver chip. Control logic All control logic (Figure 9) is implemented in the FPGAs allowing flexible usage and modifications. The design is VHDL based with further synthesis into actual FPGA. The choice of the FPGA type is driven by the functionalities needed.

L1T

L1B

FIFOout

FPGA SYNC

L1T

DAQ

FPGA VME

L1B

VME

FADC

FIFOin

FADC

FIFOin

TTC

FPGA SYNC

FIFOout

FPGA FEEM

Figure 9. Local memory There will be several FIFO on the board serving data storage and test purposes.

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Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note 3 Other prototypes functionality


3 Other prototypes functionality Prototypes for other parts of the L1 electronics will be described in details in other notes. Some ideas are presented here as initial information for other DAQ/trigger groups.

3.1 L1 vertex trigger interface (Vertex Trigger Preprocessor) The Vertex Trigger Preprocessor prepares data for the L1 trigger system (Figure 10).

MUX 32:1 Pedestal Baseline Hit subtraction correction finding (per ch) (32/128 ch)

32 Analog samples

Cluster encoding

FIFO

MUX+ format(1) N:1

MUX+ format(2) M:1

8-bit FADC 32*8

32*8 TTC

Sync

1 32*8

N input links per Read-out Module

Pedestals

VTP data

32*8 2

X*6

32*1 3

4

5

6

7

1*8 Threshold

X clusters

L1 trigger preprocessing and interface

Read-out Module

Read-out Crate

VT Link data

Figure 10. It receives 8-bit data streams from the Read-Out Module and after processing sends output data to the L1 trigger system via VT Link as shown on Figure 4. The Vertex Trigger Interface is a part of the Vertex Trigger Preprocessor in such a case. The input data format is shown on Figure 6. The requirements to the L1 trigger interface are described in [7]. Pedestal subtraction The pedestal subtraction is independent on each input data stream from the Read-Out Module. The pedestals are stored in memories - 32 values for every input link. Baseline correction The baseline correction is performed on 32 front-end chip channels (32 words in one data stream from the Read-Out Module), or on 128 channels - 4 input links. Data are stored in a FIFO during baseline calculation.

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Hit finding The hit threshold is stored in a register. After the thresholding operation, 8-bit input data are converted into 1-bit hits and so 32 8-bit words data stream into 32 1-bit words one. Position encoding Hit (cluster) position encoding may be performed on 32 front-end chip channels or involve information from neighbouring channels inside one zone of the vertex detector sector (more on that in [8]). Hit addresses are stored in FIFOs until they are read by the read-out logic. Individual events in the FIFO must be separated. Empty events are allowed. Read-out to the L1 trigger system The read-out logic sequentially reads hit addresses from FIFOs, forms a message to the L1 trigger system according to the data format specified in [7] and sends it to the L1 trigger via individual VT Link. Implementation In the final implementation all functionality of the Vertex Trigger Preprocessor may be implemented in one module, adjusting to the Read-Out Module as shown on Figure 11.

8-bit words @ 40 MHz

pedestal subtraction

hit/cluster finding position encoding

FIFO



FIFO



FIFO



FIFO

baseline correction

Control

Read-out control

VTP data

VT Link data

Figure 11. We need then Nx8 signals between them (N is a number of input links to the Read-Out Module) as shown on Figure 12 a. The pedestal subtraction, baseline correction and hit finding may be implemented in FPGA/ASIC on the Read-Out Module, then we need only Nx1 connections (Figure 12 b).

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Read-out Module N input analog links


Read-out Module VT Link


N input analog links

N*8 connections

VT Link

N*1 connections

a)

b)

Figure 12. As an extreme, all Vertex Trigger Preprocessor functionality might be implemented in the Read-Out Module if technology allows.

3.2 L1 buffer and DAQ interface This part of the L1 electronics provides event data storage during the L1 trigger latency and processing of accepted events (by Digital Signal Processors) before sending them to the DAQ system (Figure 13). L1 buffer The L1 buffer receives data from the synchronisation logic at a 40 MHz input rate. The digitized data from 4 input links are packed in 32-bit words (Figure 7). The data format also contains the full event tagging - EvID, BxID, PID, error flags. Logically, the L1 buffer is implemented as a FIFO memory of a size sufficient to store the event data during the L1 trigger latency. TTC interface The TTC receiver provides 6 bits of broadcast data with a strobe which are used to deliver a L1trigger decision to the L1 electronics. Several bits could be used to sent LSBs of the EvID from the trigger supervisor to the L1 electronics for a cross-check with the EvID stored in the L1 buffer. L1 decision logic The L1 decision logic receives the L1 decisions (accept/reject) from the TTC receiver chip in the same order as events are stored in the L1 buffer. For accepted events, data are transferred from the L1 buffer to the temporarily buffer (a L1 derandomiser or a DSP memory). For rejected events, data are simply discarded from the L1 buffer. L1 data processing The data processing after the L1 decision is performed by the DSP (pedestal subtraction,

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common mode correction, zero suppression, etc.). One DSP processes the data from a number of input links (e.g. 8 links, 256 detector channels). Each DSP accesses the event data from the temporary buffer. This buffer could be a DPM mapped to a DSP memory space. Output data are stored in other buffers.

L1 decision logic L1 decision

DPM

L1 decision logic

L1 decision logic

DPM DSP

i/f

L1 Buffer

L1 Buffer

L1 Buffer

L1 Buffer

L1 Buffer

L1 Buffer

L1Buffer data

DPM DSP

DSP

i/f

i/f

DAQ interface FE MUX data

Bus/Link

to Front-End Multiplexer (FEM)

Figure 13. Interface to the DAQ system The interface to the DAQ system (to the front-end multiplexer) provides output DSP data concentration on the read-out module level. In a case of implementation of the front-end multiplexer as a separate module in the read-out crate (Figure 3) data collection could be performed via VME bus or individual links from read-out modules to the front-end multiplexer. In a case of direct links from the read-out modules to the DAQ system (Figure 4), data collection is performed by the DAQ Read-out Unit (RU) [9].

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Vertex Detector Electronics - L1 Electronics Prototyping LHCb Technical Note 4 References


4 References [1]

LHCb. Technical proposal, CERN LHCC 98-4, LHCC/P4, 20.02.98. http://lhcb.cern.ch/technicalproposal/

[2]

Vertex Detector Electronics - Timing and Synchronisation Issues, Y.Ermoline, LHCb 98-052, TRAC, 26.06.98. http://lhcb.cern.ch/notes/postscript/98notes/98-052.ps

[3]

Event Loss Rates and Readout Chips, M.Schmelling, LHCb 98-057, TRAC, 31.8.98. http://lhcb.cern.ch/notes/postscript/98notes/98-057.ps

[4]

4 Channel Programmable Delay Chip, T.Toifl, EP/MIC.

[5]

TTCrx Reference Manual. J.Christiansen, A.Marchioro and P.Moreira, Version 2.2. http://pcvlsi5.cern.ch:80/MicDig/ttc/MANUAL22.PDF

[6]

PCF8584 I2C-bus controller, Philips Semiconductor. 21-Oct-97 http://www-eu.semiconductors.philips.com/i2c/products/

[7]

LHCb Level-1 Vertex Topology Trigger, Requirements and Interface Specification, Y.Ermoline, V.Lindenstruth, A.Mass, LHCb 99-xxx TRIG (Draft), 14.01.99.

[8]

The Vertex Detector Trigger Data Model Version 0, M.Koratzinos, LHCb 98-070 TRIG 01.02.99. http://lhcb.cern.ch/notes/postscript/98notes/98-070.pdf

[9]

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LHCb Readout Unit, H.Muller, J.Toledo.