Vertical type double gate tunnelling FETs with thin tunnel barrier
For an accurate calculation of band-to-band tunnelling (BTBT) in the source region, non-local tunnelling was used (Fig. 1).
Jang Hyun Kim, Sang Wan Kim, Hyun Woo Kim and Byung-Gook Park✉ A vertical type tunnelling field-effect transistor (TFET) with a thin tunnel junction based on a bulk Si substrate is presented. In the authors’ previously reported L-shaped TFET, a thin tunnel barrier and a large tunnelling area were employed on the source side to achieve a steep subthreshold swing (SS) and high on-current, which can lead to the TFET’s outstanding performance. The proposed TFET devices demonstrate a SS of 32 mV/decade averaged over five decades and an Ion > 10−5 A/μm. Moreover, the on-current can be increased easily by adjusting the height of the source. However, since a hump phenomenon in the transfer curves occurred, the hump behaviour in the proposed device was investigated. After investigating it, the hump behaviour was found to have originated from two different tunnelling regions. Moreover, their threshold voltages show different values. Using a capping layer that can be made by gradual doping, the hump behaviour can be suppressed.
Introduction: Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been developed for the performance by aggressive scaling down to enhance the performance. However, MOSFET scaling faces critical problems regarding power consumption. To implement low power operation, two key issues remain: reducing off-current leakage and reducing the operating voltage. The decrease of operating voltage requires scaling of threshold voltage and scalability of the subthreshold swing (SS). In a MOSFET device, the limit of SS is wellknown because the MOSFET is governed by thermal injection of carriers. The theoretical limit is 60 mV/decade in MOSFET devices and to reduce the SS to 10−5 A/μm. Acknowledgments: This work was supported by the Future Semiconductor Device Technology Development Program (10044842) funded by the Ministry of Trade, Industry and Energy (MOTIE), Korea Semiconductor Research Consortium (KSRC) and by the Brain Korea 21 Plus Project in 2014. © The Institution of Engineering and Technology 2015 6 November 2014 doi: 10.1049/el.2014.3864 One or more of the Figures in this Letter are available in colour online.
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Jang Hyun Kim, Sang Wan Kim, Hyun Woo Kim and Byung-Gook Park (Inter-university Semiconductor Research Center (ISRC), School of Nano-Science and Technology and School of Electrical Engineering, Seoul National University, San 56-1, Shillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea)
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✉ E-mail:
[email protected] References
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VG = 1.5 V VD = 0.5 V
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the on-current of the device can be enhanced by increasing the source height (Fig. 3b). In addition, it was observed in the process that the transfer curve shows a hump behaviour. This unique behaviour originated from the SEG region and the pin region, which means that there are two tunnelling junctions orthogonally the threshold voltages which are different. Thus, it was necessary to analyse the effects of tunnelling independently. To analyse the hump behaviour, BTBT rates were confirmed when the gate region was applied at 0.5 V and 1.5 V, respectively. When the gate bias was 0.5 V, BTBT was observed at the junction between the p-type layer and the intrinsic layer as shown Fig. 4. This means that, at low gate bias, BTBT at the junction between the p-type layer and the intrinsic layer (TV) can contribute to the current. However, when the gate bias is 1.5 V, the BTBT rate at the junction between the p-type layer and the SEG layer (TL) is increased more than that of TV. As a result, the transfer curve of the TFET with the SEG layer is the superposition of two tunnelling components from TL and TV (Fig. 2). To reduce the hump behaviour, the current from TV should be reduced or the threshold voltage of the TV component should be shifted to the positive direction than that from the TL component. Therefore, the gradual doping layer at the junction between the intrinsic layer and the source layer is proposed as shown in Fig. 2. By inserting the gradual doping layer, the tunnel barrier thickness is increased. In other words, electron tunnelling can occur with a very low probability when the valence band of the source and conduction band of the junction are aligned. Fig. 3a shows the transfer curves of the TFETs with the Si capping layer. In the transfer curve, the hump behaviour is not observed. Moreover, the on-current is maintained at the same level in spite of the inserted Si capping layer and the proposed structure shows a record-low SS of 32 mV/decade from 10−15 A/μm to 10−10 A/μm.
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Fig. 3 Transfer curves of the conventional TFET and the TFET with a thin tunnel barrier a Id–Vg characteristic of vertical-TFET device with and without SEG layer Device with SEG layer shows hump phenomena b Id–Vg characteristics of vertical-TFET device depending on various heights of source
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ELECTRONICS LETTERS 30th April 2015 Vol. 51 No. 9 pp. 718–720
