Voltage Regulator Module with Interleaved Synchronous Buck Converters and Novel VoltageMode Hysteretic Control* Jaber A. Abu Qahouq, Jia Luo and Issa Batarseh School of Electrical Engineering and Computer Science University of Central Florida Orlando, Florida 32816, USA
[email protected] ABSTRACT Today’s on-board low-voltage, high-current dc-dc voltage regulator module (VRM) requirements for the new generation of IC’s and microprocessors are increasingly becoming stricter than ever as the demand for high dynamic performance and high power density converters continues to increase. A new scheme that combines interleaved technique and voltage-mode hysteretic control approach, by upgrading an existing singlephase chip, will be proposed. It is expected that the new combined approach, with some design tradeoffs, will meet many of today’s VRM requirements. 1. Introduction The increasing demand for lowering the new generation microprocessors operating voltages to achieve high performance and high power density has never been greater. As a result, the steady state and dynamic requirements are becoming stricter, which makes the power supply design process a non-easy task. It is expected that the required operating voltages in the next few years will decrease below 1V while increasing the drawn current from the power supply in order to reduce the power consumption while increasing the microprocessor speed and its integration density. Moreover, the slew rate at the VRM output will be much higher than 50A/µs in the future when the microprocessor switches from one state to the other. This causes voltage drop spikes at the processor power supply. These transient spikes must be limited to a certain maximum value such as 2%~5% or even lower. As the processor supply voltage becomes lower, the allowed voltage deviation during the load transient becomes tighter [1-13]. Distributed power system can be used to satisfy overall system requirements by using on-board voltage regulator module (VRM) located near the processor. Most of today’s non-isolated Low-Voltage Regulator Modules (LVRMs) are buck derived such as the conventional buck, the synchronous buck and the Quasi-Square-Wave (QSW) buck [1,3,5,9]. While the isolated LVRMs are such as symmetrical and asymmetrical half-bridge, active clamped forward, flyback forward and push-pull [6,9]. The secondary side of the isolated topology can have different schemes such as forward, center-tapped, or current-doubler as discussed in [6]. To achieve high current slew rate at both step-up and stepdown transients, assuming that the closed loop has sufficient bandwidth, the LVRM output inductor ( Lo ) should be as small as possible. Unfortunately, using small output inductor to achieve faster transient response will cause the output voltage ripple to increase and pushes the LVRM operation towards discontinuous mode of operation. In order to reduce output voltage ripple, it is required that the switching frequency be *
Partially supported by NSF-STTR Phase I Grant # NSF-9960803.
increased. However, the higher the switching frequency, the lower the efficiency, making the selection of the switching devices very important step in the converter design process. It is also possible to reduce the output voltage ripple by increasing the output capacitor, resulting in a physically large size for practical design. In practical designs, typically the crossover frequency is designed in the range of 20%-30% of the switching frequency. Hence, the higher the switching frequency, the faster the closed loop response, resulting in smaller output capacitor and, hence, smaller critical output inductor value required to operate in the Continuous Conduction Mode (CCM). Another requirement in the design of LVRM is to have high input current slew rate that in turns require large input capacitor ( C in ). In order to decrease the size of C in , the input voltage, Vin , must be increased. This means a Distributed Power System (DPS) with high-voltage bus is needed. This makes and the isolated LVRMs more attractive than the non-isolated ones because it includes a transformer that can be used to step down the input voltage as mentioned before. In this paper, a new scheme that combines interleaved technique and voltage-mode hysteretic control approach will be proposed. It is expected that the new combined approach, with some design tradeoffs, will meet many of today’s VRM requirements. A review of the basic concept of interleaved technique is first presented, and then how hysteretic control is applied to such technique will be given. 2. Interleaving with Voltage-Mode Hysteretic Control Both the interleaving and the single-phase voltage-mode hysteretic control techniques can satisfy the output voltage ripple requirement. However, the overshoot and undershoot requirements during large magnitude transients still have to be investigated. It is known that to obtain low output overshoot, the interleaved LVRMs require the design of high-performance feedback control that can also provide current sharing [8]. Hence, even though the interleaving technique solve the ripple and fast current transient requirements, a careful control design and/or increase in the output capacitance size will be needed in order to satisfy the maximum overshoot and undershoot limits during the large load transients. In the single-phase hysteretic voltage-mode control technique, the hyteretic window can be set to a certain level such that the controller will response quickly to load transients and correct the voltage before deviating from the maximum allowed overshoot and undershoot. Even though the output capacitor size still plays an important roll here, but its size is significantly reduced because of the hysteretic window.
On one hand, the interleaving technique divides the current between the phases and allows high frequency output voltage ripple while keeping the same switching frequency for each phase. On the other hand, the hysteretic control derives its control signal from the output ripple voltage. When applying the hysteretic voltage-mode control to interleaved buck converters, one must note that: 1) The derived control signal from the output ripple (hysteretic control) must be frequency divided while keeping the same control-signal ONtime (interleaving) and 2) During the transients, this control technique must be disabled so that all the phases' switches will switch ON and OFF at the same time. The first note is to keep the switching frequency low (lower than the output voltage ripple frequency) so that the interleaving can be achieved. Whereas, the second note is to achieve faster transient response and synchronization between the phases during transients. Figure (1) shows the basic block diagram of N interleaved synchronous buck phases with voltage-mode hysteretic control while Figure (2) shows the example of control signals for two interleaved phases.
The output of the hysteretic-controlled converter is fed to the single-phase hysteretic controller. The single-phase hysteretic controller (which can be the TPS5210/TPS5211 TI Chip here [12,13]) generates the main control signal ( Cm ) which fed to the "interleaving control- pulses generation circuit". This circuit will generate the required control-signals ( C1 , C2 , …., C N ) that will feed the interleaved phases. 3.
Interleaving control-pulses generation circuit
Figure (3) shows the basic control-pulses generation circuit for two interleaved phases. The main control signal ( Cm ) from the single-phase hysteretic controller is used as an input to trigger the positive edge triggered J-K flip-flop. The two flipflop outputs are ANDed with Cm to generate the required signals ( C1 and C2 ) as shown in Figure (2). The circuit shown in Figure (3) can be upgraded to be used for larger number of interleaved phases by duplicating the same circuit repeatedly as shown in Figure (4) for four interleaved phases as an example. Figure (5) shows the preliminary experimental results for the two-phase generation circuit.
Driver Phase 1
Vin
4. Complete Controller Diagram Figure (6) shows the complete controller diagram for two phases that can be upgraded for more than two phases easily as explained in the previous section. Cm1 and Cm2 are the main control signals for the high-side and low-side MOSFETS generated by the TPS5210/TPS5211 [12,13], respectively. The control signals C1H and C2H are the generated interleaving high-side MOSFETS control signals for the two phases while C1L and C2L are the generated interleaving low-side MOSFETS control signals. The comparator "Comp1" with a reference voltage VTL is used to turn ON all the high-side MOSFETS and turn OFF all the low-side MOSFETS in the case of large low-to-high load transient, while the comparator "Comp2" with a reference voltage VTH acts in the opposite manner in the case of large high-to-low load transient.
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Interleaving Control-Pulses Generation Circuit
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Figure (1): Block Diagram
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Figure (3): Basic Control-Pulses Generation Circuit for Two Interleaved Phases (N=2)
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Figure (2): Control Signals for Two Interleaved Phases (N=2)
Figure (4): Basic Control-Pulses Generation Circuit for Four Interleaved Phases (N=4)
Figures (8) shows the simulation result for an LVRM with 12V input voltage and 1.5V output voltage with a transient current from 12A to 23A. The maximum voltage deviation at transients was ±65mV. Note that in the actual experiment, it is expected to have less deviation since the components (especially the logic gates and flip-flops) selected for the experiments are very fast while the components used in the simulation is slower (components provided by PSPICE/ORCAD was used). These simulation results were achieved by paralleling two phases only. It is expected that this design will be optimized by interleaving four-phases, which is a future work, since the current duty ratio per phase is about 0.125 and by paralleling more phases the ripple cancellation will be more effective, faster transient will be achieved since more phases will work together in transients, and higher output current can be achieved. The delays caused by the components used in the control circuit must be considered carefully. The TPS5210/TPS5211 has a delay of 250nsec. The rest of the controller parts were chosen with high speed so that the total controller delays will be much less than 400ns. 6. Conclusion Figure (5): Initial Experimental Results for the ControlPulses Generation Circuit
Figure (6): Complete Controller Diagram for Two Phases
There are always tradeoffs in satisfying certain design requirements of converter systems, and those tradeoff are more challenging when it comes to LVRM design where numerious topologies and control method constantly been introduced. Each of the known LVRM topology has its advantages and disadvantages in satisfying the increasingly strict LVRM requirements. This work focuses on combining known LVRM topology with the best control method to meet the desired future strict requirements because of the following main advantages: 1) The voltage-mode hysteretic control will track the output voltage ripple and keep it within the required limits. 2) The voltage-mode hysteretic control feedback loop doesn't need feedback loop compensation that limits the feedback loop bandwidth which limits the transient speed response. 3) The interleaving technique allows faster transient response. 4) The interleaving technique allows the sharing (division) of the load current between the phases to be realized which reduces the losses and increases the efficiency, and makes the VRM design for higher load current to be easier. 5) The interleaving technique allows lower switching frequency per phase while maintaining the same high output ripple frequency. This reduces the switching losses and hence increases the efficiency. Moreover, this simple method of achieving interleaving with hysteretic voltage-mode control can allow the additional interleaving circuit to be integrated in a single chip with the original single-phase controller chip. The simulation and initial experimental results were promising. The complete experimental prototype is currently under construction. It is expected that the new combined approach, with some design tradeoffs, will meet many of today’s VRM requirements. REFERENCES
5. LVRM Simulation Results Figure (7) shows the simulated schematics for a designed two-phase LVRM. A design example will be presented here with the following design parameters: Vin = 12V , Vo = 1.5V , I o = 23 A ,
L phase1 = L phase 2 = 1µH , and
[1].
Co = 1.5mF , with
steady-state hysteretic band of ±10mV and transient hysteretic band of ±40mV.
[2].
P. Wong, F. Lee, X. Zhou and J. Chen, “Voltage Regulator Module (VRM) Transient Modeling and Analysis,” IEEE 34th Annual Industry Applications Conference Record, IAS’99, Vol. 3, pp. 1669-1676, 1999. Intel Application Note AP-912, “Pentium III XeonTM Processor Power Distribution Guidelines,” March 1999.
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Low-Voltage Group in FloridaPEC-UCF 7404
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Document Number
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Figure (7): Simulated Schematics for a Designed Two-Phase LVRM
[6].
[7].
[8].
[9]. Figure (8): Simulation Results [3].
[4].
[5].
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[10].
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