Work-Function-Tuned TiN Metal Gate FDSOI Transistors ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 2, FEBRUARY 2011

419

Work-Function-Tuned TiN Metal Gate FDSOI Transistors for Subthreshold Operation Steven A. Vitale, Jakub Kedzierski, Paul Healey, Peter W. Wyatt, and Craig L. Keast

Abstract—The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit . Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64–80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in Cgd , and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed. Index Terms—Low power, metal gate, silicon-on-insulator (SOI), subthreshold.

I. I NTRODUCTION

U

LTRALOW-POWER transistors enable the development of electronics for energy-starved applications, such as unattended sensors, embedded medical devices, wearable electronics, and space-based devices [1]. These applications require low standby and switching power, which can be achieved by operating the transistors in the subthreshold regime, where the oncurrent is an exponential function of gate voltage. Subthreshold operation provides several benefits [2], including the following: 1) very low switching energy; 2) highest transconductance gm for a given drain current; and 3) equal NMOS and PMOS on-currents per unit width. The latter benefit allows equal NMOS and PMOS transistor widths and Cgd . Although subthreshold operation results in slower circuits, for a moderately short gate length, the operating speed is acceptable for many low-power applications. The cutoff frequency for operation is limited by the time it takes for the charge carriers to diffuse under the gate [3] and is given by fT = μUT /2πL2g , where UT is the thermal voltage (25.8 mV at room temperature) and Lg is the gate length. For a mobility of 300 cm2 /V · s and a gate length of 150 nm, one calculates fT = 6.6 GHz. Manuscript received May 3, 2010; revised October 28, 2010; accepted November 7, 2010. Date of publication December 10, 2010; date of current version January 21, 2011. This work was supported by the Air Force under Contract FA8721-05-C-0002. The review of this paper was arranged by Editor R. Huang. The authors are with the Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA 02420 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2092779

Simply lowering the operating voltage of a conventional high-performance transistor will not produce an optimized ultralow-power transistor. Conventional transistors will have comparatively high OFF-state leakage and overlap capacitance, as well as poorer subthreshold slope. These performance issues may be addressed by designing a subthreshold-optimized transistor employing a single midgap metal gate material. Fully depleted silicon-on-insulator (FDSOI) transistors with TiN metal gates have been reported for deeply scaled high-performance applications [4]–[9]. This paper complements these earlier publications by reporting the effects of processing techniques on the effective work function of the TiN metal gate. The workfunction-tuned material is then used to fabricate ultralow-power subthreshold-optimized transistors for 0.3-V operation. In this case, the transistor performance goals are given as follows: 1) maximizing subthreshold slope; 2) reducing device capacitance; 3) matching NMOS and PMOS Ion ; and 4) minimizing Vt variation. II. G ATE S TACK P ROCESSING AND W ORK F UNCTION T UNING It has been shown that an undoped silicon channel with a midgap gate electrode can be used to achieve appropriate threshold voltages [4], [10], [11]. However, without channel doping, it is necessary to tune the work function of the gate material to adjust Vt . A single midgap metal gate electrode with an effective ) of 4.65 eV should provide symmetric threshwork function (Φm old voltages for both NMOS and PMOS [12], [13], allowing equal NMOS and PMOS on-currents per unit width below Vt . TiN was chosen as the gate metal, because it is compatible with conventional CMOS processing [4]–[9]. Since low capacitance is desirable for an ultralow-power circuit and SiO2 has been shown to be compatible with a TiN metal gate [11], [14], relatively thick SiO2 is used as a gate dielectric. To characterize the TiN material and to understand the effect of process parameters on the work function of TiN, capacitors were tested on bulk silicon samples prior to FDSOI transistor fabrication. Although the work function trends are measured on bulk Si (due to lower wafer cost), the TiN properties should not change significantly when deposited on SOI substrates. Furthermore, the work-function tuning trends should be the same for FDSOI subthreshold-optimized transistors operating at 0.3 V or conventional FDSOI transistors operating at 1.2 V, although a different work function value may be optimal at 1.2-V operation due to DIBL. Capacitors measuring 1 mm2 were fabricated using a stack of 4-nm SiO2 , 20-nm TiN, 200-nm N+ polysilicon, and 250-nm

0018-9383/$26.00 © 2010 IEEE

420


Fig. 1. C–V curves with N+ polysilicon and two different TiN metal gate materials (TiN = 20 nm, 300 ◦ C, on 4.2-nm SiO2 ).

Fig. 2. TiN capacitors with and without N2 anneal. The inset is an expansion from −1 to 0 V (TiN = 20 nm, 66% N2 , 300 ◦ C, on 4.2-nm SiO2 ).

Al on p-type silicon wafers. After a 30-min forming gas anneal, 21 capacitors on each wafer were tested. Each of the data points presented is the average of these 21 measurements, unless noted. Representative C–V curves are shown in Fig. 1, comparing N+ polysilicon gates and TiN gates deposited using two different reactive sputtering conditions: 100% N2 and 67% N2 + 33% Ar. The flatband voltage increases for the metal gate material, showing that the effective work function increases. The inversion capacitance is also higher for the TiN gates, due to elimination of polysilicon depletion. The solid lines through the C–V curves are fits by a quantum-corrected capacitor model from NCSU [15], which is used to extract effective work function and equivalent oxide thickness (EOT). The effective work function Φm is related to the actual metal work function on a particular dielectric by Φm = Φm −

qNf td εd

(1)

where td and εd are the thickness and permittivity of the dielectric, respectively, and Nf is the net number of gate dielectric charges (sum of fixed and trapped charge). Postdeposition annealing in a N2 environment has been shown to reduce C–V curve hysteresis caused by gate dielectric interface states [16], [17] and to reduce gate leakage [18]. Fig. 2 shows the results of a 30-min subatmospheric 626 ◦ C N2 anneal

Fig. 3. Effective work-function change between (open symbols) annealed and (filled symbols) un-annealed capacitors, with two gate dielectric thicknesses (TiN = 20 nm, 66% N2 , 300 ◦ C).

Fig. 4. Work function of TiN metal gates as a function of %N2 gas flow (balance Ar) and substrate temperature during reactive sputter deposition (TiN = 20 nm, 66% N2 , on 4.0-nm SiO2 ).

after TiN deposition. The inset expands the region from −1 to 0 V, illustrating that the C–V curve of the unannealed wafer is stretched out slightly, suggesting the presence of interface states Dit in the dielectric [19]. The N2 anneal reduces the density of interface states and should result in improved device reliability. Wafers were processed with and without the N2 anneal, using both 4.0- and 4.3-nm gate SiO2 gate dielectric thicknesses. The effective work function and EOT values were calculated from the C–V curves, as shown in Fig. 3. The postdeposition anneal results in an increased effective work function for both gate dielectric thicknesses. The mean increase in Φm is 0.12 eV for the 4.3-nm gate dielectric and 0.05 eV with the 4.0-nm gate dielectric. The average change in EOT after N2 anneal is less than 0.2 Å, so the Φm change is most likely not due to TiO2 interlayer formation [20] or N incorporation in the dielectric [14]. It is possible that the N2 anneal increases the nitrogen content in the TiN metal gate, thus increasing the work function [14], or the anneal may reduce the gate dielectric positive charge, thus increasing Φm by (1). Fig. 3 suggests there was initially more charge in the 4.3-nm oxide, although reason for this is unclear. The effects of N2 flow and deposition temperature during reactive sputtering on effective work function are shown in Fig. 4. Although there is no significant effect of temperature on Φm ,

VITALE et al.: WORK-FUNCTION-TUNED FDSOI TRANSISTOR FOR SUBTHRESHOLD OPERATION

421

Fig. 5. SIMS depth profile of TiN/SiO2 /Si metal gate stack for various 66%–100% N2 gas flow (balance Ar) during sputter deposition. (a)–(c) With postdeposition N2 anneal. (d) No N2 anneal.

increasing N2 gas concentration decreases the effective work function. SIMS depth profiling of the TiN/SiO2 gate stack was performed to investigate if the change in Φm could be related to changes in film stoichiometry as a function of %N2 flow. The Ti, N, O, and Si depth profiles are given in Fig. 5 for three different %N2 flow conditions (all with the postdeposition N2 anneal) and one wafer without the anneal. The SIMS signal in counts was not converted to atom % due to a lack of appropriate calibration standards. The “tail” of Ti going into the SiO2 film may be indicative of some TiO2 formation, although it is most likely a result of knock-on of Ti into the SiO2 during depth profiling. Careful comparison between Fig. 5(a)–(c) shows nearly identical elemental depth profiles for all three %N2 flow conditions. (On 0% and 40% N2 flow samples, there is much lower N content by SIMS, as expected.) Furthermore, in comparing Fig. 5(a) and (d), there is no change in elemental depth profile due to the 626 ◦ C N2 anneal. This suggests that the observed changes in Φm as a function of %N2 gas flow and N2 annealing are not a result of gross changes in TiN stoichiometry. Alternative causes for decreasing Φm include lower film stress or dielectric charge, which will be addressed in a future work. Fig. 6 shows that the EOT of the capacitors is basically unchanged (< 1 Å) as the N2 flow increases for two different starting SiO2 thicknesses measured by ellipsometer. The very modest decrease in EOT with increasing %N2 may be due to additional sputtering of the gate dielectric during the early stages of TiN deposition since the SIMS data in Fig. 5(a)–(c) show no change in N profile in the gate dielectric as %N2 gas flow changes. Effective work function has been shown to be a function of metal gate thickness [17], [21], so capacitors with TiN films

Fig. 6. EOT of TiN/SiO2 capacitors as a function of %N2 gas flow (balance Ar) and substrate temperature during reactive sputter deposition for 4.0- and 4.3-nm starting SiO2 . TiN = 20 nm.

with 7–20-nm thickness were fabricated by changing the TiN deposition time. The effect on Φm is given in Fig. 7. Effective work function decreases as the TiN thickness increases, although the decrease is not monotonic. To understand the relationship between TiN thickness and work function, it is important to distinguish between the effective work function (Φm ) and the work function in the absence of gate dielectric charge (Φm ), which are related by (1). By measuring Vfb of capacitors with differing gate dielectric thicknesses, the interface charge and Φm can be calculated independently by Vf b = Φm − ΦSi −

qNf EOT εd

(2)

422


Fig. 7. Effective work function as a function of TiN thickness (TiN = 66% N2 , 300 ◦ C, with N2 anneal on 4.2-nm SiO2 ). TABLE I GATE PROPERTIES AS A FUNCTION OF TiN THICKNESS

where ΦSi = 4.93 eV is the work function of the p-type bulk Si (B-doped 7 × 1014 cm−3 ). Capacitors were fabricated with SiO2 thicknesses from 6 to 8 nm, and the results for different TiN thickness are provided in Table I. There are two competing effects as the TiN thickness increases. From 7 to 12 nm, Φm increases rapidly, leading to the high in Φm at 12 nm in Fig. 7. This may be due to a rapidly changing TiN grain structure or even surface coverage quality for these very thin films. From 12 to 20 nm, the effect of increasing gate dielectric positive charge is greater than the modest further increase in Φm , so the effective work function falls, as seen in Fig. 7. Note that, with an ALD TiN, for which there is less effect expected from charge incorporation, increasing Φm with thickness has also been reported [21]. Increasing positive charge with increasing TiN thickness could be due to more gate dielectric damage during the longer sputtering time [22] or due to increased strain at the SiO2 /TiN [16], [18]. Film stress was measured for each TiN thickness and is compressive and constant at 3.8 ± 0.4 GPa. Thus, the strain at the TiN/SiO2 interface will increase linearly with TiN thickness, so film stress is a possible cause for the increasing fixed charge. Fig. 8 shows normal probability plots of effective work function as a function of deposited TiN thickness. Capacitors were measured at each thickness. There is much less Φm variation for thinner TiN, with an optimum around 10-nm thickness. As the TiN thickness decreases from 20 to 10 nm, the standard deviation of effective work function drops from 0.021 to 0.007 eV. It is preferred to reduce the thickness of the TiN to reduce Vt variation and possible reliability issues. However, the

Fig. 8. Normal probability plots of Φm extracted from C–V curves, as a function of TiN metal gate thickness. The numbers in parentheses are the standard deviation of the data in electronvolts (TiN = 66% N2 , 300 ◦ C, with N2 anneal on 4.2-nm SiO2 ).

Fig. 9. Difference in effective work function between gates with N+ and P+ polysilicon over TiN metal gate, as a function of TiN thickness (TiN = 66% N2 , 300 ◦ C, with N2 anneal on 4.0-nm SiO2 ).

gate metal must remain thick enough to provide a uniform film across the wafer and to serve as an effective barrier to boron penetration [22]. The effect of doping the polysilicon layer of the gate stack was investigated by implanting either P (8 keV, 3.5 × 1015 ions/cm2 ) or B (6 keV, 1.0 × 1015 ions/cm2 ). The workfunction difference between the n- and p-type implanted gate is shown in Fig. 9. Very little difference is observed, implying that either the TiN is an effective diffusion barrier to these dopants or the work function of TiN is not affected by B or P doping. Therefore, doping is not likely to be used for TiN metal gate tuning. A summary of the effects of these process parameters on the effective work function of the metal gate is provided in Table II. The target work-function value of 4.65 eV is obtained by using 12-nm physical vapor deposition (PVD) TiN, deposited using 74 sccm N2 and 36 sccm Ar at 300 ◦ C, on 4.2 nm SiO2 gate dielectric, followed by a 30-min 626 ◦ C N2 anneal (see Fig. 7). A lot-to-lot work-function variation of ±0.03 eV is observed, however.


423

TABLE II TiN EFFECTIVE WORKFUNCTION TUNING

Fig. 11. Representative TiN metal gate ultralow-power transistor I–V curves (Lg = 180 nm, W = 8 μm). Devices show very good subthreshold performance and work-function tuning.

Fig. 10. Schematic comparison of traditional and subthreshold-optimized FDSOI transistor designs.

III. S UBTHRESHOLD T RANSISTOR P ROCESS I NTEGRATION Using the TiN gate material previously developed, FDSOI transistors were fabricated using 40-nm Si on 400-nm BOX. For ultralow-power subthreshold operation, the threshold voltage variation and the capacitance must be kept to a minimum. A schematic comparison between traditional and subthresholdoptimized FDSOI transistor design is shown in Fig. 10. Capacitance is minimized by eliminating the source and drain extension implants, using wide 90-nm nitride spacers and a relatively thick 4-nm SiO2 gate dielectric. However, because of the gate-to-source/drain (S/D) underlap, device resistance will be high, and the on-current in saturation will be low. Such a device architecture is not appropriate for high-performance transistors. However, for low-speed ultralow-power transistors in subthreshold operation, the on-current is limited by the subthreshold swing and not by the parasitic resistance. Since Ion is an exponential function of transistor threshold voltage in subthreshold operation, Vt control is particularly important. The subthreshold-optimized ultralow-power transistors should have much improved Vt variation, because the absence of channel, extension, and halo doping will eliminate S/D extension variations upon annealing, reduce Vt rolloff due longer Leﬀ , eliminate random dopant fluctuations, and reduce dependence on SOI thickness. The integration includes a 10-s 1022 ◦ C activation anneal, Co silicide, a 20-min 400 ◦ C hydrogen passivation anneal, and three levels of metal. The minimum gate length is 150 nm due to limitations of the 248-nm stepper used for patterning.

Fig. 12. Subthreshold swing increases from near ideal at long gate lengths to ∼80 mV/dec at Lg = 150 nm due to SCEs (W = 8 μm).

NMOS and PMOS transistor Id –Vg characteristics are shown in Fig. 11. Although the intended operating voltage is Vg = 0.3 V, the extended Id –Vg curve out to Vg = 1.5 V is provided to demonstrate that the transistors show normal above-threshold behavior. The closely matched NMOS and PMOS Ion and Ioﬀ performance demonstrates that the TiN work-function tuning performed on bulk Si wafers does not change significantly for FDSOI devices. The subthreshold swing (S) in Fig. 12 is nearideal for long gate lengths and increases to 75–80-mV/dec as the gate length decreases due to short-channel effects (SCEs). S for NMOS is higher than PMOS, because the NMOS S/D implant diffuses laterally 20 nm farther into the underlap region than the PMOS S/D implant (based on Cgd data, not shown). The NMOS channel is thus 40 nm shorter than PMOS for a given drawn gate length. The SCEs can be improved significantly by further reducing the SOI thickness [11]. It was previously shown that work-function control is improved and gate dielectric charge is reduced as the TiN metal gate thickness is decreased. Fig. 13 compares S for 12- and 20-nm TiN. The subthreshold swing is reduced by ∼5 mV/dec

424


Fig. 15. PMOS experimental I–V characteristics from 21 die on two different wafers. The wafer with the underlapped ultralow-power architecture shows significantly tighter Vt distribution.

Fig. 13. Normal probability plots of (a) NMOS and (b) PMOS subthreshold swing for L = 150 nm, W = 8 μm subthreshold-optimized transistors with 12- and 20-nm-thick TiN metal gates.

Fig. 14. PMOS/NMOS on-current at Vd = Vg = 0.3 V. Error bars represent one standard deviation assuming a log normal distribution.

for both NMOS and PMOS when the thinner TiN is used. In addition, the variation in S is lower with a 12-nm TiN gate. Because the subthreshold swing is somewhat better on PMOS transistors than NMOS transistors, the PMOS is slightly stronger. Fig. 14 shows that the P/N on-current ratio is still close

Fig. 16. Gate-to-S/D overlap capacitance measured on 180-nm (W = 100 μm) PMOS transistors. The subthreshold-optimized underlap design reduces capacitance by 71%, in agreement with ATLAS device simulation (dashed lines).

to 1, as desired, although it is a challenge to maintain this value across long and short gate lengths due to Vt rolloff. Fig. 15 compares the PMOS Id –Vg characteristics of 21 die on two wafers: one with body, extension, and halo doping (conventional transistors) and one without those implant steps (ultralow-power transistors). In this case, the transistors were fabricated with polysilicon gates, so the threshold voltage is shifted by one-half of the band gap. The subthresholdoptimized design provides an across-wafer Vt distribution (3σ) of 8 mV, compared with 18 mV for the conventional transistors. Reduced capacitance is a key performance advantage of the ultralow-power transistor design. The overlap capacitance was measured on ultralow-power transistors and conventional transistors and compared with ATLAS simulation results. As shown in Fig. 16, the measured data are in good agreement with the simulations. The ultralow-power FDSOI transistor provides a 71% reduction in overlap capacitance, compared with a transistor with a conventional FDSOI design.


IV. C ONCLUSION The effects of process parameters on the effective work function of a midgap TiN metal gate material have been studied, and the results have been integrated into the fabrication of subthreshold-optimized ultralow-power transistors. Nitrogen gas flow during deposition, postdeposition annealing, and TiN thickness all affect Φm . Thinner TiN also significantly reduces the variation in Φm and gate dielectric charge. The effective work function of the TiN metal gate was shown to be tunable through the range of 4.30–4.65 eV by adjusting the preceding process parameters. However, the results suggest that there is a significant effect from gate dielectric charge arising from TiN PVD, so it may be preferable to investigate a different deposition method such as ALD. The work-function-tuned TiN metal gates were integrated into a subthreshold-optimized transistor design. The following performance metrics were achieved: 64–80-mV/dec subthreshold swing, 71% reduction in Cgd , PMOS/NMOS on-current ratio near 1, and 55% reduction in Vt variation. ACKNOWLEDGMENT Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the U.S. Government. R EFERENCES [1] B. H. Calhoun, D. C. Daly, N. Verma, D. F. Finchelstein, D. D. Wentzloff, A. Wang, S.-H. Cho, and A. P. Chandrakasan, “Design considerations for ultra-low energy wireless microsensor nodes,” IEEE Trans. Comput., vol. 54, no. 6, pp. 727–740, Jun. 2005. [2] E. Vittoz, “Micropower techniques,” in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, J. Franca and Y. Tsividis, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1994. [3] J. Yang, J. Spann, R. Anderson, and T. Thornton, “High-frequency performance of subthreshold SOI MESFETs,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 652–654, Sep. 2004. [4] C. Fenouillet-Beranger, S. Denorme, B. Icard, F. Boeuf, J. Coignus, O. Faynot, L. Brevard, C. Buj, C. Soonekindt, J. Todeschini, J. C. Le-Denmat, N. Loubet, C. Gallon, P. Perreau, S. Manakli, B. Minghetti, L. Pain, V. Arnal, A. Vandooren, D. Aime, L. Tosti, C. Savardi, F. Martin, T. Salvetat, S. Lhostis, C. Laviron, N. Auriac, T. Kormann, G. Chabanne, S. Gaillard, O. Belmont, E. Laffosse, D. Barge, A. Zauner, A. Tarnowka, K. Romanjec, H. Brut, A. Lagha, S. Bonnetier, F. Joly, N. Mayet, A. Cathignol, D. Galpin, D. Pop, R. Delsol, R. Pantel, F. Pionnier, G. Thomas, D. Bensahel, S. Deleombus, T. Skotnicki, and H. Mingam, “Fully depleted SOI technology using high-K and singlemetal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell,” in IEDM Tech. Dig., Dec. 2007, pp. 267–270. [5] F. Andrieu, C. Dupre, F. Rochette, O. Faynot, L. Tosti, C. Buj, E. Rouchouze, M. Casse, B. Ghyselen, I. Cayrefoureq, L. Brevard, F. Allain, J. C. Barbe, J. Cluzel, A. Vandooren, S. Denorme, T. Ernst, C. Fenouillet-Beranger, C. Jahan, D. Lafond, H. Dansas, B. Previtali, J. P. Colonna, H. Grampeix, P. Gaud, C. Mazure, and S. Deleonibus, “25 nm short and narrow strained FDSOI with TiN/HfO2 gate stack,” in VLSI Symp. Tech. Dig., 2006, pp. 134–135. [6] V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEDM Tech. Dig., Dec. 2007, pp. 61–64. [7] B. Doris, Y. H. Kim, B. P. Linder, M. Steen, V. Narayanan, D. Boyd, J. Rubino, L. Chang, J. Sleight, A. Topol, E. Sikorski, L. Shi, L. Wong, K. Babich, Y. Zhang, P. Kirsch, J. Newbury, J. F. Walker, R. Carruthers, C. D’Emic, P. Kozlowski, R. Jammy, K. W. Guarini, and M. Leong, “High performance FDSOI CMOS technology with metal gate and high-k,” in VLSI Symp. Tech. Dig., 2005, pp. 214–215.

425

[8] F. Andrieu, O. Faynot, X. Garros, D. Lafond, C. Buj-Dufournet, L. Tosti, S. Minoret, V. Vidal, J. C. Barbe, F. Allain, E. Rouchouze, L. Vandroux, V. Cosnier, M. Casse, V. Delaye, C. Carabasse, M. Burdin, G. Rolland, B. Guillaumot, J. P. Colonna, P. Besson, L. Brevard, D. Mariolle, P. Holliger, A. Vandooren, C. Fenouillet-Beranger, F. Martin, and S. Deleonibus, “Comparative scalability of PVD and CVD TiN on HfO2 as a metal gate stack for FDSOI cMOSFETs down to 25 nm gate length and width,” in IEDM Tech. Dig., 23.7, 2006, pp. 1–4. [9] N. Collaert, M. Demand, I. Ferain, J. Lisoni, R. Singanamalla, P. Zimmerman, Y. S. Yim, T. Schram, G. Mannaert, M. Goodwin, J. C. Hooker, F. Neuilly, M. C. Kim, K. De Meyer, S. De Gendt, W. Boullart, M. Jurezak, and S. Biesemans, “Tall triple-gate devices with TiN/HfO2 gate stack,” in VLSI Symp. Tech. Dig., 2005, pp. 108–109. [10] H. Shang and M. H. White, “An ultra-thin midgap gate FDSOI MOSFET,” Solid State Electron., vol. 44, no. 9, pp. 1621–1625, Sep. 2000. [11] J. Chen, B. Maiti, D. Connelly, M. Mendicino, F. Huang, O. Adetutu, Y. Yu, D. Weddington, W. Wu, J. Canelaria, D. Dow, P. Tobin, and J. Mogab, “0.18 μm metal gate fully-depleted SOI MOSFETs for advanced CMOS applications,” in VLSI Symp. Tech. Dig., 1999, pp. 25–26. [12] Y. Liu, S. Kijima, E. Sugimata, M. Masahara, K. Endo, T. Matsukawa, K. Ishii, K. Sakamoto, T. Sekigawa, H. Yamauchi, Y. Takanashi, and E. Suzuki, “Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication,” IEEE Trans. Nanotechnol., vol. 5, no. 6, pp. 723–730, Nov. 2006. [13] R. Singanamalla, J. Lisoni, I. Ferain, O. Richard, L. Carbonell, T. Schram, H. Y. Yu, S. Kubicek, S. De Gendt, M. Jurczak, and K. De Meyer, “Electrical and material evaluation of the MOCVD TiN as metal gate electrode for advanced CMOS technology,” in Proc. Mater. Res. Soc. Symp., 2006, vol. 917, pp. 174–197. [14] S. C. Song, Z. Zhang, S. H. Bae, P. Kirsch, P. Majhi, R. Choi, and B. H. Lee, “High performance metal gate CMOSFETs with aggressively scaled Hf-based high-k,” ECS Trans., vol. 1, pp. 609–623, 2006. [15] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling study of ultrathin gate oxides using direct tunneling current and capacitancevoltage measurements in MOS devices,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1464–1471, Jul. 1999. [16] R. Li and Q. Xu, “Damascene W/TiN gate MOSFETs with improved performance for 0.1- μm regime,” IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1891–1896, Nov. 2002. [17] J. H. Jang, S. H. Hong, T. J. Park, J. H. Heo, S. R. Yang, M. Y. Kim, and C. S. Hwang, “Improvement in thermal stability of MOCVD HfO2 films using and ALD SiNx interfacial layer,” ECS Trans., vol. 1, pp. 393–397, 2006. [18] C.-C. Chen, H.-C. Lin, C.-Y. Chang, T.-S. Chao, T.-Y. Huang, and M.-S. Liang, “Plasma-process-induced damage in sputter TiN metal-gate capacitors with ultrathin nitrided oxides,” Jpn. J. Appl. Phys., vol. 39, no. 8, pp. 4733–4737, Aug. 2000. [19] S.-W. Huang and J.-G. Hwu, “Indication of lateral nonuniformity of effective oxide charges in high-k gate dielectrics by Terman’s method,” ECS Trans., vol. 1, pp. 789–796, 2006. [20] Y. Kuroki, J.-A. Ng, K. Kakushima, N. Sugii, K. Tsutsui, and H. Iwai, “ Al/La2 O3 analysis of post metallization annealed MISFETs by XPS,” ECS Trans., vol. 1, pp. 239–247, 2006. [21] K. Choi, P. Lysaght, H. Alshareef, C. Huffman, H.-C. Wen, R. Harris, H. Luan, P.-Y. Hung, C. Sparks, M. Cruz, K. Matthews, P. Majhi, and B. H. Lee, “Growth mechanism of TiN film on dielectric films and the effects on the work function,” Thin Solid Films, vol. 486, no. 1/2, pp. 141– 144, Aug. 2005. [22] S. H. Bae, S.-C. Song, K. Choi, G. Bersuker, G. A. Brown, D.-L. Kwong, and B. H. Lee, “Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric,” Microelectron. Eng., vol. 83, no. 3, pp. 460–462, Mar. 2006. Steven A. Vitale received the B.S. degree in chemical engineering from Johns Hopkins University, Baltimore, MD, and the M.S. degree in nuclear engineering and the Ph.D. degree in chemical engineering from Massachusetts Institute of Technology (MIT), Cambridge. From 2001 to 2007, he was a Technical Staff member with Texas Instruments, Dallas, developing plasma processes for the 90–45-nm technology nodes. In 2007, he became a Technical Staff member with Lincoln Laboratory, MIT, Lexington, and is currently pursuing research activities in the Advanced Silicon Technology Group, focused on ultralow-power electronics, microelectron beam arrays, and novel plasma processes.

426


Jakub Kedzierski received the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 2001. Following his graduation, he joined IBM’s T. J. Watson Research Center, Yorktown Heights, NY, working on advanced silicon devices. In 2005, he moved to Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, where he is currently the Assistant Group Leader in the Advanced Silicon Technology Group. His research interests include FinFETs, silicon nanowires, fully silicided gates, metal source–drains, and fully depleted silicon-on-insulator technology. His current research interests include graphene transistors, low-power electronics, and electrocapillary microfluidics.

Peter W. Wyatt received the B.S. degree from California Institute of Technology (Caltech), Pasadena, and the Ph.D. degree from Yale, New Haven, CT. Prior to joining Lincoln Laboratory, Massachusetts Institute of Technology (MIT), Lexington, in 1977, he worked for several years at Bell Laboratories, on tantalum thin-film integrated circuits. He is currently a Senior Member of Technical Staff with the Advanced Silicon Technology Group, with particular interest in silicon-on-insulator (SOI) transistor fabrication, modeling, and testing. He led the efforts at Lincoln Laboratory in wafer-scale integration and in SPICE model development for fully depleted SOI transistors.

Paul Healey received the M.S. degree in electrical engineering from the University of Connecticut, Storrs, in 1994, with his thesis focused on the realization of II–VI compound laser diodes. From 1995 to 2002, he worked in the semiconductor capital equipment industry, primarily in the process application development and integration areas. In 2003, he joined the Advanced Silicon Technology Group, Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, where his work is concentrated on the development of novel processes for the fabrication of advanced microelectronic devices and circuits.

Craig L. Keast received the B.A. degree from Hamilton College, Clinton, NY, and the S.M., E.E., and Ph.D. degrees in electrical engineering and computer science from Massachusetts Institute of Technology (MIT), Cambridge. He is currently the Associate Head of the Solid State Division and the Director of Operations for the Microelectronics Laboratory, Lincoln Laboratory, MIT, Lexington. From 1981 to 1988, he was with Lincoln Laboratory, where he worked on semiconductor processing and technology development for the Digital Wafer-Scale Electronics Group. After completing the Ph.D. degree, in 1992, he returned to Lincoln Laboratory, where he first worked with the Submicrometer Technology Group on deeply scaled device development using advanced optical lithography techniques. His current research interests include deep-submicrometer low-power CMOS process development, RF and optical MEMS, and 3-D circuit integration technologies.