WorldAcademics
World Academics Journal of Engineering Sciences ____________________________________________________________ World Acad. J. Eng. Sci. 01 2008 (2014) doi:10.15449/wjes.2014.2008
ISSN: 2348-635X
Novel Circuit Technique for Low Power CMOS design Vaibhav Neema E&TC Engg Dept., Institute of Engineering and Technology, DAVV, Indore, India. Email:
[email protected] Abstract: while some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and determine the effects of dual threshold voltage over five leakage power savings techniques: Sleep Transistor, Sleepy Stack Transistor, Sleep Keeper, LECTOR and Our Proposed technique (VSECURE).Two Input NAND gate is consider as a base case for assessment of above mentioned technique using Tanner EDA tool. In this research work effect of dual threshold voltage over static power dissipation, dynamic power dissipation and on propagation delay is experimentally observe using predictive technology 90n m models. Keywords: Standby mode, Dual threshold voltage subthreshold leakage current.
Introduction With the ever growing demand for low power high performance battery operated systems, device dimensions and operating voltages are constantly being reduced. In order to prevent the negative effect on performance incurred, the threshold voltage (Vth ) must be reduced at the same rate such that a sufficient gate overdrive is maintained [1]. This reduction in the threshold voltage causes up to a 5 leakage current increase per generation [2] Figure 1, which in turn, can increase the static power of the device to unacceptable levels. This results in increased standby power in mobile and handheld systems.
Fig 1. Leakage currents in Nanoscale transistor.
Leakage estimation and reduction therefore are becoming increasingly important. Many techniques have been proposed to achieve leakage power reduction. So me require mod ification of the process technology, achieving leakage reduction during the fabrication/ design stage, while others are based on circuit -level optimization schemes that require architectural support, and in some cases, technology support as well, but are applied at run-time. So me popular technology/fabrication techniques include the following: mu ltip le threshold CMOS (MTCM OS) [3]; silicon on insulator (SOI) [4]; finFET [5]; and multigate structure [6]. The evaluations of the practicability of the techniques dual threshold are done. Throughout the evaluation, we would like to emphasize the importance of using “minimu m id le time,” which is the minimu m t ime for a circu it to stay in the sleep mode so that the power saving can be gained when considering the overheads associated with the leakage reduction techniques, as a metric for evaluating these leakage reduction techniques. The rest of the paper is organized as follo ws. In Section II we review sources of power dissipation Section III, we briefly describe the most common ly used leakage reduction techniques. In Section IV, experimental methodology and results of our study while Sect ion V presents the results of study and Section VI concludes this work.
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Sources of Power Dissipation
VT =
The power consumed by CMOS circu its can be classified into two categories: Dynamic Power Dissipation For a fract ion of an instant during the operation of a circuit, both the PMOS and NMOS devices are “on” simu ltaneously. The duration of the interval depends on the input and output transition (rise and fall) times. During this time, a path exists between Vdd and Gnd and a short-circuit current flows. However, this is not the dominant factor in dynamic power dissipation. The major co mponent of dynamic power dissipation arises from t ransient switching behavior of the nodes. Signals in CM OS devices transition back and forth between the two logic levels, resulting in the charging and discharging of parasitic capacitances in the circuit. Dynamic power dissipation is proportional to the square of the supply voltage. Every t ime a capacitive node (CL ) switches fro m Vdd to Gnd (and back), energy of CL Vdd 2 is consumed. In deep-submicron processes, supply voltages and threshold voltages for MOS transistors are greatly reduced. This, to an extent, reduces the dynamic power dissipation. Static Power Dissipation This is the power dissipation due to leakage currents which flo w through a transistor when no transactions occur and the transistor is in a steady state. Leakage power depends on gate length and oxide thickness. It varies exponentially with threshold voltage and other parameters. Reduction of supply voltages and threshold voltages for MOS t ransistors, which helps to reduce dynamic power d issipation, becomes disadvantageous in this case. The Subthreshold leakage current increases exponentially, thereby increasing static power dissipation. Subthreshold Leakage Current: A MOSFET operates in the weak inversion (Subthreshold) region when the magnitude of the gate to source voltage is less then the magnitude of the threshold voltage [3].in the week inversion mode, current conduction between source and drain is primarily due to diffusion of the carriers [7][8].the transistor off state (Isubthreshold ) is the drain current when the gate to source voltage is zero. The exponential relat ion between driving voltage on the gate and the IOFF current is a straight line in the semilog plot of Isubthreshold versus VGS. Weak inversion current typically do minates modern device off state leakage due to the low Vth . the week inversion current can be expressed based on the following Equation(1) [8].
I Subthreshold =
µWCox L
V
2
T
e
VGS −Vth nVT
(1 − e
−VDS VT
) (1)
kT q
(2) Where μ is the carries mobility, W is the Transistor width, Co x is the oxide capacitance per unit area, VT is the thermal voltage, VGS is the gate to source voltage, Vth is the threshold voltage, n is the Subthreshold swing coefficient, Vdd is the drain to source voltage, k is the Boltzmann Constant, T is the absolute temperature (K), q it the unit charge. Propagation delay in CMOS circuit is define as equation 3
td =
VDD (VDD − VTH )α
(3) Where td is the delay, Vdd is the supply voltage and Vth is the threshold voltage. Table 1. Dependence of Subthreshol d Current on transistor parameters [11] Parameter Dependence Transistor width (W) Directly Proportional Transistor Length (L) Inversely Proportional Temperature (T) Exponential Inverse Threshold Increases with scaling Vo ltage(Vth) of Vth Input Vo ltage (VGS) Exponential Increases Drain to Source voltage Exponential Increases It is observed from table 1 that for the low subthreshold leakage power reduction, optimal transistor sizing is essential. Another important parameter is threshold voltage of transistor. The Vdd supply voltage is continuously scaled with technology nodes; from the equation 3 the delay of the circuit is inversely proportional to the Vdd supply voltage. Due to the reduction of Vdd supply voltage the delay of the circuit is continuously increasing, to maintain the performance of the circuit at Nanometer technology nodes, the threshold voltage must be scaled . As the threshold voltage is scaling the subthreshold voltage swing is increasing, so that subthreshold leakage power d issipation is increases. Means as we scale the transistor size in Nanoscale region (below to 180n m) the high leakage power is dissipated
Literature review of low Leakage Techniques Basic Two input NAND gate: For assessment of different low leakage techniques we consider two input CMOS NAND gate shown in Figure 2, as a base case. In CMOS NAND gate parallel combination of PM OS and series comb ination of NMOS is present respectively in pull up network and pull down network.
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overcome with the disadvantages of Sleep and Stack transistor techniques. This circuit will work in t wo different modes as shown in figure 10. Active mode: during the active mode signal S is at logic low hence both sleep transistors are ON. With parallel to the sleep transistors two more transistors are ON or OFF according to the input and provide parallel path to flow of current so that the overall delay of the circuit will reduces in active mode. Sleep Mode: during the sleep mode signal S is at logic high, so that both sleep transistors are in OFF state. And two parallel transistors are in OFF or ON state will depend on input applied voltage, so the output is not in the floating state and it is capable to store the pervious state of the circuit Fig 2. Two input NAND Gate. Basic Two input NAND gate: Figure 3 show the implementation of two input CM OS NAND gate using Sleepy Transistor technique, two additional transistors called Sleep transistor are add to reduce the leakage power dissipation of the CMOS circuit. This circuit will work in two modes of operations Active mode: In active mode of operation sleep signal in at logic low, so that both sleep transistors are on and circuit behave like basic CM OS circuit Idle mode: In this mode of operation the sleep signal is at logic h igh value, so that both the sleep transistors are in off state with high threshold voltage. Because of off state of sleep transistor leakage current through these transistor is very small and it will reduces leakage power dissipation of the CMOS circu it.
Fig 3. Sleepy Transistor Technique for two Input NAND gate [9] Sleepy Stack Transistor Technique: Figure 5 show the two input NAND gate using Sleepy Stack Transistor technique, this technique is the combination of Sleep transistor and Stack transistor techniques. By using this technique we can
Fig 4. Sleepy stack Transistor two input NAND gate [9]. Sleep Keeper Technique : Figure 6 show the two input NAND gate using Sleepy Stack Transistor technique, The basic problem with tradit ional CMOS is that the transistors are used only in their most efficient, and naturally inverting, way: namely, PM OS transistors connect to Vdd and NMOS transistors connect to Gnd. It is well known that PMOS transistors are not efficient at passing Gnd; similarly, it is well known that NMOS transistors are not efficient at passing Vdd However, to maintain a value of ‘1’ in sleep mode, given that the ‘1’ value has already been calculated, the sleepy keeper approach uses this output value of ‘1’ and an NMOS transistor connected to Vdd to maintain output value equal to ‘1’ when in sleep mode. As shown in Figure 6, an additional single NM OS transistor placed in parallel to the pull-up sleep transistor connects Vdd to the pull-up network. When in sleep mode, this NMOS transistor is the only source of Vdd to the pull-up network since the sleep transistor is off.
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VSECURE p roposed Technique Figure 7 show the proposed two input NAND gate using VSECURE technique, In this technique leakage current is reduces by using two additional transistors (one PMOS and one NMOS). In active mode of operation when sleep signal is “low” then sleep PMOS is in ON state and NMOS is in OFF state , hence circu it perform normal operat ion. During Sleep mode , Sleep signal is at active high state , hence PMOS sleep transistor is in OFF state. OFF state PMOS cutoff Node V1 to Vout node, means leakage current only flows through this transistor. During sleep mode NMOS transistor is in ON state hence it will provide non floating output.
Fig 5. Sleepy keeper two input NAND gate [10] Similarly, to maintain a value of ‘0’ in sleep mode, given that the ‘0’ value has already been calculated, the sleepy keeper approach uses this output value of ‘0’ and a PMOS transistor connected to Gnd to maintain output value equal to ‘0’ when in sleep mode. As shown in Figure 6, an additional single PMOS transistor placed in parallel to the pulldown sleep transistor is the only source of Gnd to the pull-down network wh ich is the dual case of the output ‘1’ case exp lained above. LECTOR Technique : Figure 6 show the two input NAND gate using Sleepy Stack Transistor technique, In this technique leakage current is reduces by adapting the technique of effective stacking of transistors. Two Leakage Control Transistors (LCTs), LCT1 and LCT2, are introduced between nodes N1 and N2. The gate terminal for each LCT is controlled by the source of the other. Hence, these LCTs act as self-controlled stacked transistors. No external control circu itry is required using the LECTOR imp lementation. The introduction of LCTs increases the resistance of the path from Vdd to Gnd, thereby reducing leakage
Fig 6. LECTOR t wo input NAND gate [11]
Fig 7. VSECURE two input NAND gate
Experimental Results
Methodology and
In order to find dual threshold effect over existing low power techniques and over our proposed technique, Schemat ics for all models and approaches are created in TANNER Schematic Ed itor [12] and sized them according to mentioned W/L ratio in Table 2. Netlists are extracted fro m the schematic using T-SPICE. These netlists are augmented with parameters extracted fro m the predictive technology Model 90n m process, (Table 1). All considered approaches are evaluated for performance by using a single, low-Vth for all transistors. Dual Vth technology is applied as mentioned in Table 1 and tested. The high-Vth is set to have 2.0 times higher Vth than the Vth of a normal transistor (low-Vth ). Before running TSPICE, the netlists are modified to d istinguish two different Vth values. For examp le, ‘NMOSH’ and ‘PMOSH’ are used to indicate high-Vth and ‘NMOS’ and ‘PMOS’ are used for low-Vth. Input vectors and input and output triggers are chosen to measure delay across a given circuit’s critical path. Fall time is measured as the time between the trigger input edge reaching 50% supply voltage and circuit output edge falling to 50% supply
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Dynamic Power Dissipation
1.00E-07 1.00E-08
Graph 2 Dynamic Power Dissipation (W) Propagation Delay (Sec)
Ba se
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1.00E-02
ee p
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1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12
Graph 1 Static Po wer Dissipation (W)
tra ns i
st st or Sl or ee (D p ua St l St VT ac a k H ck Tr ) tra an ns sis is to t o r( Sl r Du ee al p St VT ac Sl H k ) ee Tr p an Ke sis pe to r( r Du al VT Sl H) ee p Ke ep er LE CT VS O R VC EC EL U RE AR (w I T VS ith EC hi gh U RE N M O S VT H)
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Ca se tra tra ns n s is ist or Sl to r ee (D p ua St lV St ac T a kT H) ck ra tra ns ns is t is t or o Sl r (D ee ua p lV St TH ac Sl kT ) ee p ra Ke ns is t pe or r( Du al VT Sl H) ee p Ke ep er LE CT VS OR VC EC EL UR AR E (w IT VS ith EC hig UR hN E M OS VT H)
1.00E+00
ua lV St TH ac k Tr ) tra an ns sis is to t o r( Sl r Du ee al p St VT ac Sl H k ) ee Tr p an Ke sis pe to r( r Du al VT Sl H) ee p Ke ep er LE CT VS O R VC EC EL U RE AR (w I T VS ith EC hi gh U RE N M O S VT H)
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Static Power Dissipation (W)
St ac k
ee p
1.00E-05
1.00E-04
Scaling down of the CMOS technology feature size and threshold voltage for achieving high performance has resulted in increase of leakage power dissipation, but this leakage power can be control by using high threshold voltage transistor. Graph 1 shows that for leakage reduction use of dual threshold circuit topology is more effect ive as compare to simp le one threshold voltage circuit topology. The VSECURE our proposed technique with dual threshold is most effective circuit technique for reduction in leakage current. From graph 2, 3 it is clear that use of high threshold circuit technique reduces leakage current with small in dynamic power dissipation and delay penalty.
st or Sl
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Conclusion
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voltage. Likewise, the time between the input edge reaching 50% and circuit output edge rising to 50% supply voltage is recorded as the rise time. This method of measuring delay is carried on throughout all experiments, with only the high/low patterns of the input vectors varying and triggers varying. Dynamic power is measured by asserting clocked semi-random input vectors for a period of 20ns and calculating the average power dissipated during this period. Static power is measured by asserting a set of input vectors as DC sources in TSPICE and measuring the average power dissipated by the circuit during a period of 20 ns. Figure 1,2 , 3 and Tab le 4 shows the effect of Dual Threshold voltage transistor over Static power dissipation (graph -1 ) , dynamic power d issipation (Graph -2) , Propagation Delay (Graph-3) , power delay product (PDP) static ( Table 4 column 5) and power delay product (PDP) dynamic ( Table 4, Colu mn -6).
Neema
1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12
Graph 3 Propagation Delay (Sec)
References [1] FALLA H, F., AND PEDRAM, M. Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits. IEICE Transactions on Electronics, Special Section on Low-Po wer LSI and Low-Power IP E88-C, 4 (April 2005), 509–519. [2] BORKA R, S. Gigascale Integration Challenges and Opportunities (Ho me > Intel Software Network Strategies & Technologies). [3] M. W. Allam, M. H. Anis, and M. I. Elmasry, “High-Speed Dynamic Log ic Sty les for ScaledDown CM OS and MTCM OS Technologies,” Proceedings of the IEEE International Symposiu m on Low-Power Electronics Design, pp. 155–160, July 2000. [4] S. M itra et al., “Lo w Vo ltage/Low Po wer Sub 50n m Double Gate SOI Ratioed Logic,” Proceedings of the IEEE International SOI Conference, pp.177-178, September 2003. [5] F. Dauge, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jo maah, B.-Y. Nguyen, “Coupling effects and channels separation in FinFETs”, in So lid -State Electronics, vol. 48, no. 4, pp. 535-542, April 2004.
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[6] B. S. Doyle et al. “High Performance FullyDepleted Tri-Gate CM OS Transistors,” IEEE electron Device Letters, Vo l. 24, No. 4, pp. 263265, April 2003. [7] Roy K, Prasad SC. Low-Power CM OS VLSI Circuit Design. John Wiley & Sons, Inc. 2000. [8] Ferre A, Figueras J. (September 1998). Characterizat ion of leakage power in CM OS technologies. Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, pp. 185– 188. [9] J. Park, V. J. Mooney, and P. Pfeiffenberger, “Sleepy stack reduction in leakage power,” in
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Proc. Int.Workshop Power Timing Modeling, Optimiz. Simulat ion, 2004, pp. 148–158. [10] Se Hun Kim , Vincent J. Mooney III, " Sleep Keeper : a New Approch to Leakage Power VLSI Design. [11] HANCHATE, N., AND RA NGA NATHAN, N. LECTOR: A Technique for Leakage Reduction in CM OS Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, 2 (February 2004), 196–205. [12] Tanner EDA tool, http://www.tanner.co m.
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